1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
39#include "params/SparcDTB.hh"
40#include "params/SparcITB.hh"
41#include "sim/faults.hh"
42#include "sim/tlb.hh"
43
44class ThreadContext;
45class Packet;
46
47namespace SparcISA
48{
49
50class TLB : public BaseTLB
51{
52#if !FULL_SYSTEM
53 //These faults need to be able to populate the tlb in SE mode.
54 friend class FastInstructionAccessMMUMiss;
55 friend class FastDataAccessMMUMiss;
56#endif
57
58 //TLB state
59 protected:
60 uint64_t c0_tsb_ps0;
61 uint64_t c0_tsb_ps1;
62 uint64_t c0_config;
63 uint64_t cx_tsb_ps0;
64 uint64_t cx_tsb_ps1;
65 uint64_t cx_config;
66 uint64_t sfsr;
67 uint64_t tag_access;
68
69 protected:
70 TlbMap lookupTable;;
71 typedef TlbMap::iterator MapIter;
72
73 TlbEntry *tlb;
74
75 int size;
76 int usedEntries;
77 int lastReplaced;
78
79 uint64_t cacheState;
80 bool cacheValid;
81
82 std::list<TlbEntry*> freeList;
83
84 enum FaultTypes {
85 OtherFault = 0,
86 PrivViolation = 0x1,
87 SideEffect = 0x2,
88 AtomicToIo = 0x4,
89 IllegalAsi = 0x8,
90 LoadFromNfo = 0x10,
91 VaOutOfRange = 0x20,
92 VaOutOfRangeJmp = 0x40
93 };
94
95 enum ContextType {
96 Primary = 0,
97 Secondary = 1,
98 Nucleus = 2
99 };
100
101 enum TsbPageSize {
102 Ps0,
103 Ps1
104 };
105 public:
106 /** lookup an entry in the TLB based on the partition id, and real bit if
107 * real is true or the partition id, and context id if real is false.
108 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
109 * @param paritition_id partition this entry is for
110 * @param real is this a real->phys or virt->phys translation
111 * @param context_id if this is virt->phys what context
112 * @param update_used should ew update the used bits in the
113 * entries on not useful if we are trying to do a va->pa without
114 * mucking with any state for a debug read for example.
115 * @return A pointer to a tlb entry
116 */
117 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
118 bool update_used = true);
119 protected:
120 /** Insert a PTE into the TLB. */
121 void insert(Addr vpn, int partition_id, int context_id, bool real,
122 const PageTableEntry& PTE, int entry = -1);
123
124 /** Given an entry id, read that tlb entries' tag. */
125 uint64_t TagRead(int entry);
126
127 /** Remove all entries from the TLB */
128 void invalidateAll();
129
130 /** Remove all non-locked entries from the tlb that match partition id. */
131 void demapAll(int partition_id);
132
133 /** Remove all entries that match a given context/partition id. */
134 void demapContext(int partition_id, int context_id);
135
136 /** Remve all entries that match a certain partition id, (contextid), and
137 * va). */
138 void demapPage(Addr va, int partition_id, bool real, int context_id);
139
140 /** Checks if the virtual address provided is a valid one. */
141 bool validVirtualAddress(Addr va, bool am);
142
143 void writeSfsr(bool write, ContextType ct,
144 bool se, FaultTypes ft, int asi);
145
146 void clearUsedBits();
147
148
149 void writeTagAccess(Addr va, int context);
150
151 public:
152 typedef SparcTLBParams Params;
153 TLB(const Params *p);
154
155 void demapPage(Addr vaddr, uint64_t asn)
156 {
157 panic("demapPage(Addr) is not implemented.\n");
158 }
159
160 void dumpAll();
161
162 // Checkpointing
163 virtual void serialize(std::ostream &os);
164 virtual void unserialize(Checkpoint *cp, const std::string §ion);
165
166 /** Give an entry id, read that tlb entries' tte */
167 uint64_t TteRead(int entry);
168
169};
170
171class ITB : public TLB
172{
173 public:
174 typedef SparcITBParams Params;
175 ITB(const Params *p) : TLB(p)
176 {
177 cacheEntry = NULL;
178 }
179
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
39#include "params/SparcDTB.hh"
40#include "params/SparcITB.hh"
41#include "sim/faults.hh"
42#include "sim/tlb.hh"
43
44class ThreadContext;
45class Packet;
46
47namespace SparcISA
48{
49
50class TLB : public BaseTLB
51{
52#if !FULL_SYSTEM
53 //These faults need to be able to populate the tlb in SE mode.
54 friend class FastInstructionAccessMMUMiss;
55 friend class FastDataAccessMMUMiss;
56#endif
57
58 //TLB state
59 protected:
60 uint64_t c0_tsb_ps0;
61 uint64_t c0_tsb_ps1;
62 uint64_t c0_config;
63 uint64_t cx_tsb_ps0;
64 uint64_t cx_tsb_ps1;
65 uint64_t cx_config;
66 uint64_t sfsr;
67 uint64_t tag_access;
68
69 protected:
70 TlbMap lookupTable;;
71 typedef TlbMap::iterator MapIter;
72
73 TlbEntry *tlb;
74
75 int size;
76 int usedEntries;
77 int lastReplaced;
78
79 uint64_t cacheState;
80 bool cacheValid;
81
82 std::list<TlbEntry*> freeList;
83
84 enum FaultTypes {
85 OtherFault = 0,
86 PrivViolation = 0x1,
87 SideEffect = 0x2,
88 AtomicToIo = 0x4,
89 IllegalAsi = 0x8,
90 LoadFromNfo = 0x10,
91 VaOutOfRange = 0x20,
92 VaOutOfRangeJmp = 0x40
93 };
94
95 enum ContextType {
96 Primary = 0,
97 Secondary = 1,
98 Nucleus = 2
99 };
100
101 enum TsbPageSize {
102 Ps0,
103 Ps1
104 };
105 public:
106 /** lookup an entry in the TLB based on the partition id, and real bit if
107 * real is true or the partition id, and context id if real is false.
108 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
109 * @param paritition_id partition this entry is for
110 * @param real is this a real->phys or virt->phys translation
111 * @param context_id if this is virt->phys what context
112 * @param update_used should ew update the used bits in the
113 * entries on not useful if we are trying to do a va->pa without
114 * mucking with any state for a debug read for example.
115 * @return A pointer to a tlb entry
116 */
117 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
118 bool update_used = true);
119 protected:
120 /** Insert a PTE into the TLB. */
121 void insert(Addr vpn, int partition_id, int context_id, bool real,
122 const PageTableEntry& PTE, int entry = -1);
123
124 /** Given an entry id, read that tlb entries' tag. */
125 uint64_t TagRead(int entry);
126
127 /** Remove all entries from the TLB */
128 void invalidateAll();
129
130 /** Remove all non-locked entries from the tlb that match partition id. */
131 void demapAll(int partition_id);
132
133 /** Remove all entries that match a given context/partition id. */
134 void demapContext(int partition_id, int context_id);
135
136 /** Remve all entries that match a certain partition id, (contextid), and
137 * va). */
138 void demapPage(Addr va, int partition_id, bool real, int context_id);
139
140 /** Checks if the virtual address provided is a valid one. */
141 bool validVirtualAddress(Addr va, bool am);
142
143 void writeSfsr(bool write, ContextType ct,
144 bool se, FaultTypes ft, int asi);
145
146 void clearUsedBits();
147
148
149 void writeTagAccess(Addr va, int context);
150
151 public:
152 typedef SparcTLBParams Params;
153 TLB(const Params *p);
154
155 void demapPage(Addr vaddr, uint64_t asn)
156 {
157 panic("demapPage(Addr) is not implemented.\n");
158 }
159
160 void dumpAll();
161
162 // Checkpointing
163 virtual void serialize(std::ostream &os);
164 virtual void unserialize(Checkpoint *cp, const std::string §ion);
165
166 /** Give an entry id, read that tlb entries' tte */
167 uint64_t TteRead(int entry);
168
169};
170
171class ITB : public TLB
172{
173 public:
174 typedef SparcITBParams Params;
175 ITB(const Params *p) : TLB(p)
176 {
177 cacheEntry = NULL;
178 }
179
|
203#if FULL_SYSTEM
204 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
205 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
206#endif
207 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
208
209 // Checkpointing
210 virtual void serialize(std::ostream &os);
211 virtual void unserialize(Checkpoint *cp, const std::string §ion);
212
213 private:
214 void writeSfsr(Addr a, bool write, ContextType ct,
215 bool se, FaultTypes ft, int asi);
216
217 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
218 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
219
220
221 TlbEntry *cacheEntry[2];
222 ASI cacheAsi[2];
223};
224
225}
226
227#endif // __ARCH_SPARC_TLB_HH__
| 208#if FULL_SYSTEM
209 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
210 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
211#endif
212 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
213
214 // Checkpointing
215 virtual void serialize(std::ostream &os);
216 virtual void unserialize(Checkpoint *cp, const std::string §ion);
217
218 private:
219 void writeSfsr(Addr a, bool write, ContextType ct,
220 bool se, FaultTypes ft, int asi);
221
222 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
223 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
224
225
226 TlbEntry *cacheEntry[2];
227 ASI cacheAsi[2];
228};
229
230}
231
232#endif // __ARCH_SPARC_TLB_HH__
|