1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
|
| 37#include "config/full_system.hh"
|
37#include "mem/request.hh"
38#include "sim/faults.hh"
39#include "sim/sim_object.hh"
40
41class ThreadContext;
42class Packet;
43
44namespace SparcISA
45{
46
47class TLB : public SimObject
48{
| 38#include "mem/request.hh"
39#include "sim/faults.hh"
40#include "sim/sim_object.hh"
41
42class ThreadContext;
43class Packet;
44
45namespace SparcISA
46{
47
48class TLB : public SimObject
49{
|
| 50#if !FULL_SYSTEM
51 //These faults need to be able to populate the tlb in SE mode.
52 friend class FastInstructionAccessMMUMiss;
53 friend class FastDataAccessMMUMiss;
54#endif
55
|
49 //TLB state
50 protected:
51 uint64_t c0_tsb_ps0;
52 uint64_t c0_tsb_ps1;
53 uint64_t c0_config;
54 uint64_t cx_tsb_ps0;
55 uint64_t cx_tsb_ps1;
56 uint64_t cx_config;
57 uint64_t sfsr;
58 uint64_t tag_access;
59
60 protected:
61 TlbMap lookupTable;;
62 typedef TlbMap::iterator MapIter;
63
64 TlbEntry *tlb;
65
66 int size;
67 int usedEntries;
68 int lastReplaced;
69
70 uint64_t cacheState;
71 bool cacheValid;
72
73 std::list<TlbEntry*> freeList;
74
75 enum FaultTypes {
76 OtherFault = 0,
77 PrivViolation = 0x1,
78 SideEffect = 0x2,
79 AtomicToIo = 0x4,
80 IllegalAsi = 0x8,
81 LoadFromNfo = 0x10,
82 VaOutOfRange = 0x20,
83 VaOutOfRangeJmp = 0x40
84 };
85
86 enum ContextType {
87 Primary = 0,
88 Secondary = 1,
89 Nucleus = 2
90 };
91
92 enum TsbPageSize {
93 Ps0,
94 Ps1
95 };
96 public:
97 /** lookup an entry in the TLB based on the partition id, and real bit if
98 * real is true or the partition id, and context id if real is false.
99 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
100 * @param paritition_id partition this entry is for
101 * @param real is this a real->phys or virt->phys translation
102 * @param context_id if this is virt->phys what context
103 * @param update_used should ew update the used bits in the entries on not
104 * useful if we are trying to do a va->pa without mucking with any state for
105 * a debug read for example.
106 * @return A pointer to a tlb entry
107 */
108 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
109 bool update_used = true);
110 protected:
111 /** Insert a PTE into the TLB. */
112 void insert(Addr vpn, int partition_id, int context_id, bool real,
113 const PageTableEntry& PTE, int entry = -1);
114
115 /** Given an entry id, read that tlb entries' tag. */
116 uint64_t TagRead(int entry);
117
118 /** Remove all entries from the TLB */
119 void invalidateAll();
120
121 /** Remove all non-locked entries from the tlb that match partition id. */
122 void demapAll(int partition_id);
123
124 /** Remove all entries that match a given context/partition id. */
125 void demapContext(int partition_id, int context_id);
126
127 /** Remve all entries that match a certain partition id, (contextid), and
128 * va). */
129 void demapPage(Addr va, int partition_id, bool real, int context_id);
130
131 /** Checks if the virtual address provided is a valid one. */
132 bool validVirtualAddress(Addr va, bool am);
133
134 void writeSfsr(bool write, ContextType ct,
135 bool se, FaultTypes ft, int asi);
136
137 void clearUsedBits();
138
139
140 void writeTagAccess(Addr va, int context);
141
142 public:
143 TLB(const std::string &name, int size);
144
145 void dumpAll();
146
147 // Checkpointing
148 virtual void serialize(std::ostream &os);
149 virtual void unserialize(Checkpoint *cp, const std::string §ion);
150
151 /** Give an entry id, read that tlb entries' tte */
152 uint64_t TteRead(int entry);
153
154};
155
156class ITB : public TLB
157{
158 public:
159 ITB(const std::string &name, int size) : TLB(name, size)
160 {
161 cacheEntry = NULL;
162 }
163
164 Fault translate(RequestPtr &req, ThreadContext *tc);
165 private:
166 void writeSfsr(bool write, ContextType ct,
167 bool se, FaultTypes ft, int asi);
168 TlbEntry *cacheEntry;
169 friend class DTB;
170};
171
172class DTB : public TLB
173{
174 //DTLB specific state
175 protected:
176 uint64_t sfar;
177 public:
178 DTB(const std::string &name, int size) : TLB(name, size)
179 {
180 sfar = 0;
181 cacheEntry[0] = NULL;
182 cacheEntry[1] = NULL;
183 }
184
185 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
| 56 //TLB state
57 protected:
58 uint64_t c0_tsb_ps0;
59 uint64_t c0_tsb_ps1;
60 uint64_t c0_config;
61 uint64_t cx_tsb_ps0;
62 uint64_t cx_tsb_ps1;
63 uint64_t cx_config;
64 uint64_t sfsr;
65 uint64_t tag_access;
66
67 protected:
68 TlbMap lookupTable;;
69 typedef TlbMap::iterator MapIter;
70
71 TlbEntry *tlb;
72
73 int size;
74 int usedEntries;
75 int lastReplaced;
76
77 uint64_t cacheState;
78 bool cacheValid;
79
80 std::list<TlbEntry*> freeList;
81
82 enum FaultTypes {
83 OtherFault = 0,
84 PrivViolation = 0x1,
85 SideEffect = 0x2,
86 AtomicToIo = 0x4,
87 IllegalAsi = 0x8,
88 LoadFromNfo = 0x10,
89 VaOutOfRange = 0x20,
90 VaOutOfRangeJmp = 0x40
91 };
92
93 enum ContextType {
94 Primary = 0,
95 Secondary = 1,
96 Nucleus = 2
97 };
98
99 enum TsbPageSize {
100 Ps0,
101 Ps1
102 };
103 public:
104 /** lookup an entry in the TLB based on the partition id, and real bit if
105 * real is true or the partition id, and context id if real is false.
106 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
107 * @param paritition_id partition this entry is for
108 * @param real is this a real->phys or virt->phys translation
109 * @param context_id if this is virt->phys what context
110 * @param update_used should ew update the used bits in the entries on not
111 * useful if we are trying to do a va->pa without mucking with any state for
112 * a debug read for example.
113 * @return A pointer to a tlb entry
114 */
115 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
116 bool update_used = true);
117 protected:
118 /** Insert a PTE into the TLB. */
119 void insert(Addr vpn, int partition_id, int context_id, bool real,
120 const PageTableEntry& PTE, int entry = -1);
121
122 /** Given an entry id, read that tlb entries' tag. */
123 uint64_t TagRead(int entry);
124
125 /** Remove all entries from the TLB */
126 void invalidateAll();
127
128 /** Remove all non-locked entries from the tlb that match partition id. */
129 void demapAll(int partition_id);
130
131 /** Remove all entries that match a given context/partition id. */
132 void demapContext(int partition_id, int context_id);
133
134 /** Remve all entries that match a certain partition id, (contextid), and
135 * va). */
136 void demapPage(Addr va, int partition_id, bool real, int context_id);
137
138 /** Checks if the virtual address provided is a valid one. */
139 bool validVirtualAddress(Addr va, bool am);
140
141 void writeSfsr(bool write, ContextType ct,
142 bool se, FaultTypes ft, int asi);
143
144 void clearUsedBits();
145
146
147 void writeTagAccess(Addr va, int context);
148
149 public:
150 TLB(const std::string &name, int size);
151
152 void dumpAll();
153
154 // Checkpointing
155 virtual void serialize(std::ostream &os);
156 virtual void unserialize(Checkpoint *cp, const std::string §ion);
157
158 /** Give an entry id, read that tlb entries' tte */
159 uint64_t TteRead(int entry);
160
161};
162
163class ITB : public TLB
164{
165 public:
166 ITB(const std::string &name, int size) : TLB(name, size)
167 {
168 cacheEntry = NULL;
169 }
170
171 Fault translate(RequestPtr &req, ThreadContext *tc);
172 private:
173 void writeSfsr(bool write, ContextType ct,
174 bool se, FaultTypes ft, int asi);
175 TlbEntry *cacheEntry;
176 friend class DTB;
177};
178
179class DTB : public TLB
180{
181 //DTLB specific state
182 protected:
183 uint64_t sfar;
184 public:
185 DTB(const std::string &name, int size) : TLB(name, size)
186 {
187 sfar = 0;
188 cacheEntry[0] = NULL;
189 cacheEntry[1] = NULL;
190 }
191
192 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
|
| 193#if FULL_SYSTEM
|
186 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
187 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
| 194 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
195 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
|
| 196#endif
|
188 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
189
190 // Checkpointing
191 virtual void serialize(std::ostream &os);
192 virtual void unserialize(Checkpoint *cp, const std::string §ion);
193
194 private:
195 void writeSfsr(Addr a, bool write, ContextType ct,
196 bool se, FaultTypes ft, int asi);
197
198 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
199 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
200
201
202 TlbEntry *cacheEntry[2];
203 ASI cacheAsi[2];
204};
205
206}
207
208#endif // __ARCH_SPARC_TLB_HH__
| 197 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
198
199 // Checkpointing
200 virtual void serialize(std::ostream &os);
201 virtual void unserialize(Checkpoint *cp, const std::string §ion);
202
203 private:
204 void writeSfsr(Addr a, bool write, ContextType ct,
205 bool se, FaultTypes ft, int asi);
206
207 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
208 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
209
210
211 TlbEntry *cacheEntry[2];
212 ASI cacheAsi[2];
213};
214
215}
216
217#endif // __ARCH_SPARC_TLB_HH__
|