1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
|
| 34#include "arch/sparc/asi.hh"
|
34#include "arch/sparc/tlb_map.hh"
35#include "base/misc.hh"
36#include "mem/request.hh"
37#include "sim/faults.hh"
38#include "sim/sim_object.hh"
39
40class ThreadContext;
41class Packet;
42
43namespace SparcISA
44{
45
46class TLB : public SimObject
47{
48 protected:
49 TlbMap lookupTable;;
50 typedef TlbMap::iterator MapIter;
51
52 TlbEntry *tlb;
53
54 int size;
55 int usedEntries;
56
| 35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "mem/request.hh"
38#include "sim/faults.hh"
39#include "sim/sim_object.hh"
40
41class ThreadContext;
42class Packet;
43
44namespace SparcISA
45{
46
47class TLB : public SimObject
48{
49 protected:
50 TlbMap lookupTable;;
51 typedef TlbMap::iterator MapIter;
52
53 TlbEntry *tlb;
54
55 int size;
56 int usedEntries;
57
|
| 58 uint64_t cacheState;
59 bool cacheValid;
60
|
57 enum FaultTypes {
58 OtherFault = 0,
59 PrivViolation = 0x1,
60 SideEffect = 0x2,
61 AtomicToIo = 0x4,
62 IllegalAsi = 0x8,
63 LoadFromNfo = 0x10,
64 VaOutOfRange = 0x20,
65 VaOutOfRangeJmp = 0x40
66 };
67
68 enum ContextType {
69 Primary = 0,
70 Secondary = 1,
71 Nucleus = 2
72 };
73
74
75 /** lookup an entry in the TLB based on the partition id, and real bit if
76 * real is true or the partition id, and context id if real is false.
77 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
78 * @param paritition_id partition this entry is for
79 * @param real is this a real->phys or virt->phys translation
80 * @param context_id if this is virt->phys what context
81 * @return A pointer to a tlb entry
82 */
83 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
84
85 /** Insert a PTE into the TLB. */
86 void insert(Addr vpn, int partition_id, int context_id, bool real,
87 const PageTableEntry& PTE, int entry = -1);
88
89 /** Given an entry id, read that tlb entries' tag. */
90 uint64_t TagRead(int entry);
91
92 /** Give an entry id, read that tlb entries' tte */
93 uint64_t TteRead(int entry);
94
95 /** Remove all entries from the TLB */
96 void invalidateAll();
97
98 /** Remove all non-locked entries from the tlb that match partition id. */
99 void demapAll(int partition_id);
100
101 /** Remove all entries that match a given context/partition id. */
102 void demapContext(int partition_id, int context_id);
103
104 /** Remve all entries that match a certain partition id, (contextid), and
105 * va). */
106 void demapPage(Addr va, int partition_id, bool real, int context_id);
107
108 /** Checks if the virtual address provided is a valid one. */
109 bool validVirtualAddress(Addr va, bool am);
110
111 void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
112 bool se, FaultTypes ft, int asi);
113
| 61 enum FaultTypes {
62 OtherFault = 0,
63 PrivViolation = 0x1,
64 SideEffect = 0x2,
65 AtomicToIo = 0x4,
66 IllegalAsi = 0x8,
67 LoadFromNfo = 0x10,
68 VaOutOfRange = 0x20,
69 VaOutOfRangeJmp = 0x40
70 };
71
72 enum ContextType {
73 Primary = 0,
74 Secondary = 1,
75 Nucleus = 2
76 };
77
78
79 /** lookup an entry in the TLB based on the partition id, and real bit if
80 * real is true or the partition id, and context id if real is false.
81 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
82 * @param paritition_id partition this entry is for
83 * @param real is this a real->phys or virt->phys translation
84 * @param context_id if this is virt->phys what context
85 * @return A pointer to a tlb entry
86 */
87 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
88
89 /** Insert a PTE into the TLB. */
90 void insert(Addr vpn, int partition_id, int context_id, bool real,
91 const PageTableEntry& PTE, int entry = -1);
92
93 /** Given an entry id, read that tlb entries' tag. */
94 uint64_t TagRead(int entry);
95
96 /** Give an entry id, read that tlb entries' tte */
97 uint64_t TteRead(int entry);
98
99 /** Remove all entries from the TLB */
100 void invalidateAll();
101
102 /** Remove all non-locked entries from the tlb that match partition id. */
103 void demapAll(int partition_id);
104
105 /** Remove all entries that match a given context/partition id. */
106 void demapContext(int partition_id, int context_id);
107
108 /** Remve all entries that match a certain partition id, (contextid), and
109 * va). */
110 void demapPage(Addr va, int partition_id, bool real, int context_id);
111
112 /** Checks if the virtual address provided is a valid one. */
113 bool validVirtualAddress(Addr va, bool am);
114
115 void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
116 bool se, FaultTypes ft, int asi);
117
|
114 void clearUsedBits();
| 118 void TLB::clearUsedBits();
|
115
116
117 void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);
118
119 public:
120 TLB(const std::string &name, int size);
121
122 void dumpAll();
123
124 // Checkpointing
125 virtual void serialize(std::ostream &os);
126 virtual void unserialize(Checkpoint *cp, const std::string §ion);
127};
128
129class ITB : public TLB
130{
131 public:
132 ITB(const std::string &name, int size) : TLB(name, size)
133 {
| 119
120
121 void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);
122
123 public:
124 TLB(const std::string &name, int size);
125
126 void dumpAll();
127
128 // Checkpointing
129 virtual void serialize(std::ostream &os);
130 virtual void unserialize(Checkpoint *cp, const std::string §ion);
131};
132
133class ITB : public TLB
134{
135 public:
136 ITB(const std::string &name, int size) : TLB(name, size)
137 {
|
| 138 cacheEntry = NULL;
|
134 }
135
136 Fault translate(RequestPtr &req, ThreadContext *tc);
137 private:
138 void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
139 bool se, FaultTypes ft, int asi);
140 void writeTagAccess(ThreadContext *tc, Addr va, int context);
| 139 }
140
141 Fault translate(RequestPtr &req, ThreadContext *tc);
142 private:
143 void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
144 bool se, FaultTypes ft, int asi);
145 void writeTagAccess(ThreadContext *tc, Addr va, int context);
|
| 146 TlbEntry *cacheEntry;
|
141 friend class DTB;
142};
143
144class DTB : public TLB
145{
146 public:
147 DTB(const std::string &name, int size) : TLB(name, size)
148 {
| 147 friend class DTB;
148};
149
150class DTB : public TLB
151{
152 public:
153 DTB(const std::string &name, int size) : TLB(name, size)
154 {
|
| 155 cacheEntry[0] = NULL;
156 cacheEntry[1] = NULL;
|
149 }
150
151 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
152 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
153 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
154
155 private:
156 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
157 bool se, FaultTypes ft, int asi);
158 void writeTagAccess(ThreadContext *tc, Addr va, int context);
159
| 157 }
158
159 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
160 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
161 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
162
163 private:
164 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
165 bool se, FaultTypes ft, int asi);
166 void writeTagAccess(ThreadContext *tc, Addr va, int context);
167
|
160
| 168 TlbEntry *cacheEntry[2];
169 ASI cacheAsi[2];
|
161};
162
163}
164
165#endif // __ARCH_SPARC_TLB_HH__
| 170};
171
172}
173
174#endif // __ARCH_SPARC_TLB_HH__
|