1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "base/misc.hh"
35#include "mem/request.hh"
36#include "sim/faults.hh"
37#include "sim/sim_object.hh"
38
39class ThreadContext;
40
41namespace SparcISA
42{
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "base/misc.hh"
35#include "mem/request.hh"
36#include "sim/faults.hh"
37#include "sim/sim_object.hh"
38
39class ThreadContext;
40
41namespace SparcISA
42{
|
43 class TLB : public SimObject
44 {
45 public:
46 TLB(const std::string &name, int size) : SimObject(name)
47 {
48 }
49 };
50
51 class ITB : public TLB
52 {
53 public:
54 ITB(const std::string &name, int size) : TLB(name, size)
55 {
56 }
57
58 Fault translate(RequestPtr &req, ThreadContext *tc) const
59 {
60 //For now, always assume the address is already physical.
61 //Also assume that there are 40 bits of physical address space.
| 46 class TLB : public SimObject
47 {
48 public:
49 TLB(const std::string &name, int size) : SimObject(name)
50 {
51 }
52 };
53
54 class ITB : public TLB
55 {
56 public:
57 ITB(const std::string &name, int size) : TLB(name, size)
58 {
59 }
60
61 Fault translate(RequestPtr &req, ThreadContext *tc) const
62 {
63 //For now, always assume the address is already physical.
64 //Also assume that there are 40 bits of physical address space.
|
63 return NoFault;
64 }
65 };
66
67 class DTB : public TLB
68 {
69 public:
70 DTB(const std::string &name, int size) : TLB(name, size)
71 {
72 }
73
74 Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const
75 {
76 //For now, always assume the address is already physical.
77 //Also assume that there are 40 bits of physical address space.
78 req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1));
79 return NoFault;
80 }
81 };
82}
83
84#endif // __ARCH_SPARC_TLB_HH__
| 66 return NoFault;
67 }
68 };
69
70 class DTB : public TLB
71 {
72 public:
73 DTB(const std::string &name, int size) : TLB(name, size)
74 {
75 }
76
77 Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const
78 {
79 //For now, always assume the address is already physical.
80 //Also assume that there are 40 bits of physical address space.
81 req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1));
82 return NoFault;
83 }
84 };
85}
86
87#endif // __ARCH_SPARC_TLB_HH__
|