tlb.hh (4070:74449a198a44) | tlb.hh (4990:38d74405ddac) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41class ThreadContext; 42class Packet; 43 44namespace SparcISA 45{ 46 47class TLB : public SimObject 48{ | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 32 unchanged lines hidden (view full) --- 41class ThreadContext; 42class Packet; 43 44namespace SparcISA 45{ 46 47class TLB : public SimObject 48{ |
49 //TLB state |
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49 protected: | 50 protected: |
51 uint64_t c0_tsb_ps0; 52 uint64_t c0_tsb_ps1; 53 uint64_t c0_config; 54 uint64_t cx_tsb_ps0; 55 uint64_t cx_tsb_ps1; 56 uint64_t cx_config; 57 uint64_t sfsr; 58 uint64_t tag_access; 59 60 protected: |
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50 TlbMap lookupTable;; 51 typedef TlbMap::iterator MapIter; 52 53 TlbEntry *tlb; 54 55 int size; 56 int usedEntries; 57 int lastReplaced; --- 57 unchanged lines hidden (view full) --- 115 116 /** Remve all entries that match a certain partition id, (contextid), and 117 * va). */ 118 void demapPage(Addr va, int partition_id, bool real, int context_id); 119 120 /** Checks if the virtual address provided is a valid one. */ 121 bool validVirtualAddress(Addr va, bool am); 122 | 61 TlbMap lookupTable;; 62 typedef TlbMap::iterator MapIter; 63 64 TlbEntry *tlb; 65 66 int size; 67 int usedEntries; 68 int lastReplaced; --- 57 unchanged lines hidden (view full) --- 126 127 /** Remve all entries that match a certain partition id, (contextid), and 128 * va). */ 129 void demapPage(Addr va, int partition_id, bool real, int context_id); 130 131 /** Checks if the virtual address provided is a valid one. */ 132 bool validVirtualAddress(Addr va, bool am); 133 |
123 void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, | 134 void writeSfsr(bool write, ContextType ct, |
124 bool se, FaultTypes ft, int asi); 125 126 void clearUsedBits(); 127 128 | 135 bool se, FaultTypes ft, int asi); 136 137 void clearUsedBits(); 138 139 |
129 void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context); | 140 void writeTagAccess(Addr va, int context); |
130 131 public: 132 TLB(const std::string &name, int size); 133 134 void dumpAll(); 135 136 // Checkpointing 137 virtual void serialize(std::ostream &os); --- 9 unchanged lines hidden (view full) --- 147 public: 148 ITB(const std::string &name, int size) : TLB(name, size) 149 { 150 cacheEntry = NULL; 151 } 152 153 Fault translate(RequestPtr &req, ThreadContext *tc); 154 private: | 141 142 public: 143 TLB(const std::string &name, int size); 144 145 void dumpAll(); 146 147 // Checkpointing 148 virtual void serialize(std::ostream &os); --- 9 unchanged lines hidden (view full) --- 158 public: 159 ITB(const std::string &name, int size) : TLB(name, size) 160 { 161 cacheEntry = NULL; 162 } 163 164 Fault translate(RequestPtr &req, ThreadContext *tc); 165 private: |
155 void writeSfsr(ThreadContext *tc, bool write, ContextType ct, | 166 void writeSfsr(bool write, ContextType ct, |
156 bool se, FaultTypes ft, int asi); | 167 bool se, FaultTypes ft, int asi); |
157 void writeTagAccess(ThreadContext *tc, Addr va, int context); | |
158 TlbEntry *cacheEntry; 159 friend class DTB; 160}; 161 162class DTB : public TLB 163{ | 168 TlbEntry *cacheEntry; 169 friend class DTB; 170}; 171 172class DTB : public TLB 173{ |
174 //DTLB specific state 175 protected: 176 uint64_t sfar; |
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164 public: 165 DTB(const std::string &name, int size) : TLB(name, size) 166 { | 177 public: 178 DTB(const std::string &name, int size) : TLB(name, size) 179 { |
180 sfar = 0; |
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167 cacheEntry[0] = NULL; 168 cacheEntry[1] = NULL; 169 } 170 171 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 172 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 173 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); 174 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 175 | 181 cacheEntry[0] = NULL; 182 cacheEntry[1] = NULL; 183 } 184 185 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 186 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 187 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); 188 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); 189 |
190 // Checkpointing 191 virtual void serialize(std::ostream &os); 192 virtual void unserialize(Checkpoint *cp, const std::string §ion); 193 |
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176 private: | 194 private: |
177 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, | 195 void writeSfsr(Addr a, bool write, ContextType ct, |
178 bool se, FaultTypes ft, int asi); | 196 bool se, FaultTypes ft, int asi); |
179 void writeTagAccess(ThreadContext *tc, Addr va, int context); | |
180 181 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 182 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 183 184 185 TlbEntry *cacheEntry[2]; 186 ASI cacheAsi[2]; 187}; 188 189} 190 191#endif // __ARCH_SPARC_TLB_HH__ | 197 198 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 199 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 200 201 202 TlbEntry *cacheEntry[2]; 203 ASI cacheAsi[2]; 204}; 205 206} 207 208#endif // __ARCH_SPARC_TLB_HH__ |