1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "mem/request.hh"
38#include "sim/faults.hh"
39#include "sim/sim_object.hh"
40
41class ThreadContext;
42class Packet;
43
44namespace SparcISA
45{
46
47class TLB : public SimObject
48{
49 protected:
50 TlbMap lookupTable;;
51 typedef TlbMap::iterator MapIter;
52
53 TlbEntry *tlb;
54
55 int size;
56 int usedEntries;
57 int lastReplaced;
58
59 uint64_t cacheState;
60 bool cacheValid;
61
62 std::list<TlbEntry*> freeList;
63
64 enum FaultTypes {
65 OtherFault = 0,
66 PrivViolation = 0x1,
67 SideEffect = 0x2,
68 AtomicToIo = 0x4,
69 IllegalAsi = 0x8,
70 LoadFromNfo = 0x10,
71 VaOutOfRange = 0x20,
72 VaOutOfRangeJmp = 0x40
73 };
74
75 enum ContextType {
76 Primary = 0,
77 Secondary = 1,
78 Nucleus = 2
79 };
80
81
82 /** lookup an entry in the TLB based on the partition id, and real bit if
83 * real is true or the partition id, and context id if real is false.
84 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
85 * @param paritition_id partition this entry is for
86 * @param real is this a real->phys or virt->phys translation
87 * @param context_id if this is virt->phys what context
88 * @return A pointer to a tlb entry
89 */
90 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
91
92 /** Insert a PTE into the TLB. */
93 void insert(Addr vpn, int partition_id, int context_id, bool real,
94 const PageTableEntry& PTE, int entry = -1);
95
96 /** Given an entry id, read that tlb entries' tag. */
97 uint64_t TagRead(int entry);
98
99 /** Remove all entries from the TLB */
100 void invalidateAll();
101
102 /** Remove all non-locked entries from the tlb that match partition id. */
103 void demapAll(int partition_id);
104
105 /** Remove all entries that match a given context/partition id. */
106 void demapContext(int partition_id, int context_id);
107
108 /** Remve all entries that match a certain partition id, (contextid), and
109 * va). */
110 void demapPage(Addr va, int partition_id, bool real, int context_id);
111
112 /** Checks if the virtual address provided is a valid one. */
113 bool validVirtualAddress(Addr va, bool am);
114
115 void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
116 bool se, FaultTypes ft, int asi);
117
118 void clearUsedBits();
119
120
121 void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);
122
123 public:
124 TLB(const std::string &name, int size);
125
126 void dumpAll();
127
128 // Checkpointing
129 virtual void serialize(std::ostream &os);
130 virtual void unserialize(Checkpoint *cp, const std::string &section);
131
132 /** Give an entry id, read that tlb entries' tte */
133 uint64_t TteRead(int entry);
134
135};
136
137class ITB : public TLB
138{
139 public:
140 ITB(const std::string &name, int size) : TLB(name, size)
141 {
142 cacheEntry = NULL;
143 }
144
145 Fault translate(RequestPtr &req, ThreadContext *tc);
146 private:
147 void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
148 bool se, FaultTypes ft, int asi);
149 void writeTagAccess(ThreadContext *tc, Addr va, int context);
150 TlbEntry *cacheEntry;
151 friend class DTB;
152};
153
154class DTB : public TLB
155{
156 public:
157 DTB(const std::string &name, int size) : TLB(name, size)
158 {
159 cacheEntry[0] = NULL;
160 cacheEntry[1] = NULL;
161 }
162
163 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
164 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
165 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
166
167 private:
168 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
169 bool se, FaultTypes ft, int asi);
170 void writeTagAccess(ThreadContext *tc, Addr va, int context);
171
172 TlbEntry *cacheEntry[2];
173 ASI cacheAsi[2];
174};
175
176}
177
178#endif // __ARCH_SPARC_TLB_HH__