1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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73 };
74
75 enum ContextType {
76 Primary = 0,
77 Secondary = 1,
78 Nucleus = 2
79 };
80
81
82 /** lookup an entry in the TLB based on the partition id, and real bit if
83 * real is true or the partition id, and context id if real is false.
84 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
85 * @param paritition_id partition this entry is for
86 * @param real is this a real->phys or virt->phys translation
87 * @param context_id if this is virt->phys what context
88 * @return A pointer to a tlb entry
89 */
90 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
91
92 /** Insert a PTE into the TLB. */
93 void insert(Addr vpn, int partition_id, int context_id, bool real,
94 const PageTableEntry& PTE, int entry = -1);
95
96 /** Given an entry id, read that tlb entries' tag. */
97 uint64_t TagRead(int entry);
98
99 /** Remove all entries from the TLB */

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158 {
159 cacheEntry[0] = NULL;
160 cacheEntry[1] = NULL;
161 }
162
163 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
164 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
165 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
166
167 private:
168 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
169 bool se, FaultTypes ft, int asi);
170 void writeTagAccess(ThreadContext *tc, Addr va, int context);
171
172 TlbEntry *cacheEntry[2];
173 ASI cacheAsi[2];
174};
175
176}
177
178#endif // __ARCH_SPARC_TLB_HH__