1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33
34#include "arch/sparc/tlb_map.hh"
35#include "base/misc.hh"
36#include "mem/request.hh"
37#include "sim/faults.hh"
38#include "sim/sim_object.hh"
39
40class ThreadContext;
41
42namespace SparcISA
43{
44
45class TLB : public SimObject
46{
47 protected:
48 TlbMap lookupTable;;

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137class DTB : public TLB
138{
139 public:
140 DTB(const std::string &name, int size) : TLB(name, size)
141 {
142 }
143
144 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
145
146 private:
147 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
148 bool se, FaultTypes ft, int asi);
149
150};
151
152}
153
154#endif // __ARCH_SPARC_TLB_HH__