1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 26 unchanged lines hidden (view full) ---

35#include "mem/request.hh"
36#include "sim/faults.hh"
37#include "sim/sim_object.hh"
38
39class ThreadContext;
40
41namespace SparcISA
42{
43 class TLB : public SimObject
44 {
45 public:
46 TLB(const std::string &name, int size) : SimObject(name)
47 {
48 }
49 };
50
51 class ITB : public TLB
52 {
53 public:
54 ITB(const std::string &name, int size) : TLB(name, size)
55 {
56 }
57
58 Fault translate(RequestPtr &req, ThreadContext *tc) const
59 {
60 //For now, always assume the address is already physical.
61 //Also assume that there are 40 bits of physical address space.
62 req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1));
63 return NoFault;
64 }
65 };
66
67 class DTB : public TLB
68 {
69 public:
70 DTB(const std::string &name, int size) : TLB(name, size)

--- 14 unchanged lines hidden ---