process.cc (6701:4842482e1bd1) process.cc (7532:3f6413fc37a2)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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106 "at pc %#x.\n", tc->readPC());
107 break;
108 default:
109 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
110 }
111}
112
113void
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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106 "at pc %#x.\n", tc->readPC());
107 break;
108 default:
109 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
110 }
111}
112
113void
114SparcLiveProcess::startup()
114SparcLiveProcess::initState()
115{
115{
116 Process::startup();
116 LiveProcess::initState();
117
118 ThreadContext *tc = system->getThreadContext(contextIds[0]);
119 //From the SPARC ABI
120
121 //Setup default FP state
122 tc->setMiscRegNoEffect(MISCREG_FSR, 0);
123
124 tc->setMiscRegNoEffect(MISCREG_TICK, 0);

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152 /*
153 * T1 specific registers
154 */
155 //Turn on the icache, dcache, dtb translation, and itb translation.
156 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
157}
158
159void
117
118 ThreadContext *tc = system->getThreadContext(contextIds[0]);
119 //From the SPARC ABI
120
121 //Setup default FP state
122 tc->setMiscRegNoEffect(MISCREG_FSR, 0);
123
124 tc->setMiscRegNoEffect(MISCREG_TICK, 0);

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152 /*
153 * T1 specific registers
154 */
155 //Turn on the icache, dcache, dtb translation, and itb translation.
156 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
157}
158
159void
160Sparc32LiveProcess::startup()
160Sparc32LiveProcess::initState()
161{
161{
162 if (checkpointRestored)
163 return;
162 SparcLiveProcess::initState();
164
163
165 SparcLiveProcess::startup();
166
167 ThreadContext *tc = system->getThreadContext(contextIds[0]);
168 //The process runs in user mode with 32 bit addresses
169 tc->setMiscReg(MISCREG_PSTATE, 0x0a);
170
171 argsInit(32 / 8, VMPageSize);
172}
173
174void
164 ThreadContext *tc = system->getThreadContext(contextIds[0]);
165 //The process runs in user mode with 32 bit addresses
166 tc->setMiscReg(MISCREG_PSTATE, 0x0a);
167
168 argsInit(32 / 8, VMPageSize);
169}
170
171void
175Sparc64LiveProcess::startup()
172Sparc64LiveProcess::initState()
176{
173{
177 if (checkpointRestored)
178 return;
174 SparcLiveProcess::initState();
179
175
180 SparcLiveProcess::startup();
181
182 ThreadContext *tc = system->getThreadContext(contextIds[0]);
183 //The process runs in user mode
184 tc->setMiscReg(MISCREG_PSTATE, 0x02);
185
186 argsInit(sizeof(IntReg), VMPageSize);
187}
188
189template<class IntType>

--- 385 unchanged lines hidden --- 		176 ThreadContext *tc = system->getThreadContext(contextIds[0]);
177 //The process runs in user mode
178 tc->setMiscReg(MISCREG_PSTATE, 0x02);
179
180 argsInit(sizeof(IntReg), VMPageSize);
181}
182
183template<class IntType>

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