process.cc (4793:315e1db6bd39) process.cc (4997:e7380529bd2d)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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116 threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
117 //Always use spill and fill traps 0
118 //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
119 threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
120 //Set the trap level to 0
121 threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
122 //Set the ASI register to something fixed
123 threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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116 threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
117 //Always use spill and fill traps 0
118 //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
119 threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
120 //Set the trap level to 0
121 threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
122 //Set the ASI register to something fixed
123 threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
124
125 /*
126 * T1 specific registers
127 */
128 //Turn on the icache, dcache, dtb translation, and itb translation.
129 threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
124}
125
126void
127Sparc64LiveProcess::startup()
128{
129 argsInit(sizeof(IntReg), VMPageSize);
130
131 //From the SPARC ABI
132
133 //The process runs in user mode
134 threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
135
136 //Setup default FP state
137 threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
138
139 threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
130}
131
132void
133Sparc64LiveProcess::startup()
134{
135 argsInit(sizeof(IntReg), VMPageSize);
136
137 //From the SPARC ABI
138
139 //The process runs in user mode
140 threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
141
142 //Setup default FP state
143 threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
144
145 threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
140 //
146
141 /*
142 * Register window management registers
143 */
144
145 //No windows contain info from other programs
146 //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
147 threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
148 //There are no windows to pop

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158 threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
159 //Always use spill and fill traps 0
160 //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
161 threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
162 //Set the trap level to 0
163 threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
164 //Set the ASI register to something fixed
165 threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
147 /*
148 * Register window management registers
149 */
150
151 //No windows contain info from other programs
152 //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
153 threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
154 //There are no windows to pop

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164 threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
165 //Always use spill and fill traps 0
166 //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
167 threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
168 //Set the trap level to 0
169 threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
170 //Set the ASI register to something fixed
171 threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
172
173 /*
174 * T1 specific registers
175 */
176 //Turn on the icache, dcache, dtb translation, and itb translation.
177 threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
166}
167
168M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val)
169{
170 a_type = TheISA::htog(type);
171 a_val = TheISA::htog(val);
172}
173

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179
180M5_32_auxv_t::M5_32_auxv_t(int32_t type, int32_t val)
181{
182 a_type = TheISA::htog(type);
183 a_val = TheISA::htog(val);
184}
185

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