process.cc (3760:a4fadb8ef046) process.cc (3761:b7c7f547d5a3)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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90
91 threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
92 //
93 /*
94 * Register window management registers
95 */
96
97 //No windows contain info from other programs
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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90
91 threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
92 //
93 /*
94 * Register window management registers
95 */
96
97 //No windows contain info from other programs
98 threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
98 //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0);
99 threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
99 //There are no windows to pop
100 //There are no windows to pop
100 threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
101 //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0);
102 threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0);
101 //All windows are available to save into
103 //All windows are available to save into
102 threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
104 //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2);
105 threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2);
103 //All windows are "clean"
106 //All windows are "clean"
104 threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
107 //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
108 threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows);
105 //Start with register window 0
106 threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
107 //Always use spill and fill traps 0
109 //Start with register window 0
110 threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
111 //Always use spill and fill traps 0
108 threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
112 //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
113 threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
109 //Set the trap level to 0
110 threadContexts[0]->setMiscReg(MISCREG_TL, 0);
111 //Set the ASI register to something fixed
112 threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
113}
114
115m5_auxv_t buildAuxVect(int64_t type, int64_t val)
116{

--- 315 unchanged lines hidden --- 		114 //Set the trap level to 0
115 threadContexts[0]->setMiscReg(MISCREG_TL, 0);
116 //Set the ASI register to something fixed
117 threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
118}
119
120m5_auxv_t buildAuxVect(int64_t type, int64_t val)
121{

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