process.cc (3415:72c48f292f6a) process.cc (3589:2fec1358ce80)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 15 unchanged lines hidden (view full) ---

24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#include "arch/sparc/asi.hh"
32#include "arch/sparc/isa_traits.hh"
33#include "arch/sparc/process.hh"
34#include "base/loader/object_file.hh"
35#include "base/loader/elf_object.hh"
36#include "base/misc.hh"
37#include "cpu/thread_context.hh"
38#include "mem/page_table.hh"
39#include "mem/translating_port.hh"

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100 //All windows are "clean"
101 threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
102 //Start with register window 0
103 threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
104 //Always use spill and fill traps 0
105 threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
106 //Set the trap level to 0
107 threadContexts[0]->setMiscReg(MISCREG_TL, 0);
33#include "arch/sparc/isa_traits.hh"
34#include "arch/sparc/process.hh"
35#include "base/loader/object_file.hh"
36#include "base/loader/elf_object.hh"
37#include "base/misc.hh"
38#include "cpu/thread_context.hh"
39#include "mem/page_table.hh"
40#include "mem/translating_port.hh"

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101 //All windows are "clean"
102 threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows);
103 //Start with register window 0
104 threadContexts[0]->setMiscReg(MISCREG_CWP, 0);
105 //Always use spill and fill traps 0
106 threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0);
107 //Set the trap level to 0
108 threadContexts[0]->setMiscReg(MISCREG_TL, 0);
109 //Set the ASI register to something fixed
110 threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
108}
109
110m5_auxv_t buildAuxVect(int64_t type, int64_t val)
111{
112 m5_auxv_t result;
113 result.a_type = TheISA::htog(type);
114 result.a_val = TheISA::htog(val);
115 return result;

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112
113m5_auxv_t buildAuxVect(int64_t type, int64_t val)
114{
115 m5_auxv_t result;
116 result.a_type = TheISA::htog(type);
117 result.a_val = TheISA::htog(val);
118 return result;

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