process.cc (11850:36119fa7874d) process.cc (11851:824055fe6b30)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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47#include "sim/system.hh"
48
49using namespace std;
50using namespace SparcISA;
51
52static const int FirstArgumentReg = 8;
53
54
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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47#include "sim/system.hh"
48
49using namespace std;
50using namespace SparcISA;
51
52static const int FirstArgumentReg = 8;
53
54
55SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params,
56 ObjectFile *objFile, Addr _StackBias)
57 : LiveProcess(params, objFile), StackBias(_StackBias)
55SparcProcess::SparcProcess(ProcessParams * params, ObjectFile *objFile,
56 Addr _StackBias)
57 : Process(params, objFile), StackBias(_StackBias)
58{
59
60 // XXX all the below need to be updated for SPARC - Ali
61 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
62 brk_point = roundUp(brk_point, PageBytes);
63
64 // Set pointer for next thread stack. Reserve 8M for main stack.
65 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
66
67 // Initialize these to 0s
68 fillStart = 0;
69 spillStart = 0;
70}
71
72void
58{
59
60 // XXX all the below need to be updated for SPARC - Ali
61 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
62 brk_point = roundUp(brk_point, PageBytes);
63
64 // Set pointer for next thread stack. Reserve 8M for main stack.
65 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
66
67 // Initialize these to 0s
68 fillStart = 0;
69 spillStart = 0;
70}
71
72void
73SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc)
73SparcProcess::handleTrap(int trapNum, ThreadContext *tc)
74{
75 PCState pc = tc->pcState();
76 switch (trapNum) {
77 case 0x01: // Software breakpoint
78 warn("Software breakpoint encountered at pc %#x.\n", pc.pc());
79 break;
80 case 0x02: // Division by zero
81 warn("Software signaled a division by zero at pc %#x.\n", pc.pc());

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106 "at pc %#x.\n", pc.pc());
107 break;
108 default:
109 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
110 }
111}
112
113void
74{
75 PCState pc = tc->pcState();
76 switch (trapNum) {
77 case 0x01: // Software breakpoint
78 warn("Software breakpoint encountered at pc %#x.\n", pc.pc());
79 break;
80 case 0x02: // Division by zero
81 warn("Software signaled a division by zero at pc %#x.\n", pc.pc());

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106 "at pc %#x.\n", pc.pc());
107 break;
108 default:
109 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
110 }
111}
112
113void
114SparcLiveProcess::initState()
114SparcProcess::initState()
115{
115{
116 LiveProcess::initState();
116 Process::initState();
117
118 ThreadContext *tc = system->getThreadContext(contextIds[0]);
119 // From the SPARC ABI
120
121 // Setup default FP state
122 tc->setMiscRegNoEffect(MISCREG_FSR, 0);
123
124 tc->setMiscRegNoEffect(MISCREG_TICK, 0);

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155 /*
156 * T1 specific registers
157 */
158 // Turn on the icache, dcache, dtb translation, and itb translation.
159 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
160}
161
162void
117
118 ThreadContext *tc = system->getThreadContext(contextIds[0]);
119 // From the SPARC ABI
120
121 // Setup default FP state
122 tc->setMiscRegNoEffect(MISCREG_FSR, 0);
123
124 tc->setMiscRegNoEffect(MISCREG_TICK, 0);

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155 /*
156 * T1 specific registers
157 */
158 // Turn on the icache, dcache, dtb translation, and itb translation.
159 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
160}
161
162void
163Sparc32LiveProcess::initState()
163Sparc32Process::initState()
164{
164{
165 SparcLiveProcess::initState();
165 SparcProcess::initState();
166
167 ThreadContext *tc = system->getThreadContext(contextIds[0]);
168 // The process runs in user mode with 32 bit addresses
169 PSTATE pstate = 0;
170 pstate.ie = 1;
171 pstate.am = 1;
172 tc->setMiscReg(MISCREG_PSTATE, pstate);
173
174 argsInit(32 / 8, PageBytes);
175}
176
177void
166
167 ThreadContext *tc = system->getThreadContext(contextIds[0]);
168 // The process runs in user mode with 32 bit addresses
169 PSTATE pstate = 0;
170 pstate.ie = 1;
171 pstate.am = 1;
172 tc->setMiscReg(MISCREG_PSTATE, pstate);
173
174 argsInit(32 / 8, PageBytes);
175}
176
177void
178Sparc64LiveProcess::initState()
178Sparc64Process::initState()
179{
179{
180 SparcLiveProcess::initState();
180 SparcProcess::initState();
181
182 ThreadContext *tc = system->getThreadContext(contextIds[0]);
183 // The process runs in user mode
184 PSTATE pstate = 0;
185 pstate.ie = 1;
186 tc->setMiscReg(MISCREG_PSTATE, pstate);
187
188 argsInit(sizeof(IntReg), PageBytes);
189}
190
191template<class IntType>
192void
181
182 ThreadContext *tc = system->getThreadContext(contextIds[0]);
183 // The process runs in user mode
184 PSTATE pstate = 0;
185 pstate.ie = 1;
186 tc->setMiscReg(MISCREG_PSTATE, pstate);
187
188 argsInit(sizeof(IntReg), PageBytes);
189}
190
191template<class IntType>
192void
193SparcLiveProcess::argsInit(int pageSize)
193SparcProcess::argsInit(int pageSize)
194{
195 int intSize = sizeof(IntType);
196
197 typedef AuxVector<IntType> auxv_t;
198
199 std::vector<auxv_t> auxv;
200
201 string filename;

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414
415 // Align the "stack_min" to a page boundary.
416 stack_min = roundDown(stack_min, pageSize);
417
418// num_processes++;
419}
420
421void
194{
195 int intSize = sizeof(IntType);
196
197 typedef AuxVector<IntType> auxv_t;
198
199 std::vector<auxv_t> auxv;
200
201 string filename;

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414
415 // Align the "stack_min" to a page boundary.
416 stack_min = roundDown(stack_min, pageSize);
417
418// num_processes++;
419}
420
421void
422Sparc64LiveProcess::argsInit(int intSize, int pageSize)
422Sparc64Process::argsInit(int intSize, int pageSize)
423{
423{
424 SparcLiveProcess::argsInit<uint64_t>(pageSize);
424 SparcProcess::argsInit(pageSize);
425
426 // Stuff the trap handlers into the process address space
427 initVirtMem.writeBlob(fillStart,
428 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts);
429 initVirtMem.writeBlob(spillStart,
430 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts);
431}
432
433void
425
426 // Stuff the trap handlers into the process address space
427 initVirtMem.writeBlob(fillStart,
428 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts);
429 initVirtMem.writeBlob(spillStart,
430 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts);
431}
432
433void
434Sparc32LiveProcess::argsInit(int intSize, int pageSize)
434Sparc32Process::argsInit(int intSize, int pageSize)
435{
435{
436 SparcLiveProcess::argsInit<uint32_t>(pageSize);
436 SparcProcess::argsInit(pageSize);
437
438 // Stuff the trap handlers into the process address space
439 initVirtMem.writeBlob(fillStart,
440 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts);
441 initVirtMem.writeBlob(spillStart,
442 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts);
443}
444
437
438 // Stuff the trap handlers into the process address space
439 initVirtMem.writeBlob(fillStart,
440 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts);
441 initVirtMem.writeBlob(spillStart,
442 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts);
443}
444
445void Sparc32LiveProcess::flushWindows(ThreadContext *tc)
445void Sparc32Process::flushWindows(ThreadContext *tc)
446{
447 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
448 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
449 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
450 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
451 MiscReg origCWP = CWP;
452 CWP = (CWP + Cansave + 2) % NWindows;
453 while (NWindows - 2 - Cansave != 0) {

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472 }
473 }
474 tc->setIntReg(NumIntArchRegs + 3, Cansave);
475 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
476 tc->setMiscReg(MISCREG_CWP, origCWP);
477}
478
479void
446{
447 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
448 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
449 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
450 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
451 MiscReg origCWP = CWP;
452 CWP = (CWP + Cansave + 2) % NWindows;
453 while (NWindows - 2 - Cansave != 0) {

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472 }
473 }
474 tc->setIntReg(NumIntArchRegs + 3, Cansave);
475 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
476 tc->setMiscReg(MISCREG_CWP, origCWP);
477}
478
479void
480Sparc64LiveProcess::flushWindows(ThreadContext *tc)
480Sparc64Process::flushWindows(ThreadContext *tc)
481{
482 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
483 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
484 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
485 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
486 MiscReg origCWP = CWP;
487 CWP = (CWP + Cansave + 2) % NWindows;
488 while (NWindows - 2 - Cansave != 0) {

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507 }
508 }
509 tc->setIntReg(NumIntArchRegs + 3, Cansave);
510 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
511 tc->setMiscReg(MISCREG_CWP, origCWP);
512}
513
514IntReg
481{
482 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
483 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
484 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
485 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
486 MiscReg origCWP = CWP;
487 CWP = (CWP + Cansave + 2) % NWindows;
488 while (NWindows - 2 - Cansave != 0) {

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507 }
508 }
509 tc->setIntReg(NumIntArchRegs + 3, Cansave);
510 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
511 tc->setMiscReg(MISCREG_CWP, origCWP);
512}
513
514IntReg
515Sparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i)
515Sparc32Process::getSyscallArg(ThreadContext *tc, int &i)
516{
517 assert(i < 6);
518 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0);
519}
520
521void
516{
517 assert(i < 6);
518 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0);
519}
520
521void
522Sparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val)
522Sparc32Process::setSyscallArg(ThreadContext *tc, int i, IntReg val)
523{
524 assert(i < 6);
525 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0));
526}
527
528IntReg
523{
524 assert(i < 6);
525 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0));
526}
527
528IntReg
529Sparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i)
529Sparc64Process::getSyscallArg(ThreadContext *tc, int &i)
530{
531 assert(i < 6);
532 return tc->readIntReg(FirstArgumentReg + i++);
533}
534
535void
530{
531 assert(i < 6);
532 return tc->readIntReg(FirstArgumentReg + i++);
533}
534
535void
536Sparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val)
536Sparc64Process::setSyscallArg(ThreadContext *tc, int i, IntReg val)
537{
538 assert(i < 6);
539 tc->setIntReg(FirstArgumentReg + i, val);
540}
541
542void
537{
538 assert(i < 6);
539 tc->setIntReg(FirstArgumentReg + i, val);
540}
541
542void
543SparcLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
543SparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
544{
545 // check for error condition. SPARC syscall convention is to
546 // indicate success/failure in reg the carry bit of the ccr
547 // and put the return value itself in the standard return value reg ().
548 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
549 if (sysret.successful()) {
550 // no error, clear XCC.C
551 tc->setIntReg(NumIntArchRegs + 2,

--- 15 unchanged lines hidden --- 		544{
545 // check for error condition. SPARC syscall convention is to
546 // indicate success/failure in reg the carry bit of the ccr
547 // and put the return value itself in the standard return value reg ().
548 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
549 if (sysret.successful()) {
550 // no error, clear XCC.C
551 tc->setIntReg(NumIntArchRegs + 2,

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