process.cc (11800:54436a1784dc) process.cc (11850:36119fa7874d)
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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144 // Always use spill and fill traps 0
145 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
146 tc->setIntReg(NumIntArchRegs + 7, 0);
147 // Set the trap level to 0
148 tc->setMiscRegNoEffect(MISCREG_TL, 0);
149 // Set the ASI register to something fixed
150 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
151
1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 135 unchanged lines hidden (view full) ---

144 // Always use spill and fill traps 0
145 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
146 tc->setIntReg(NumIntArchRegs + 7, 0);
147 // Set the trap level to 0
148 tc->setMiscRegNoEffect(MISCREG_TL, 0);
149 // Set the ASI register to something fixed
150 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
151
152 // Set the MMU Primary Context Register to hold the process' pid
153 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid);
154
152 /*
153 * T1 specific registers
154 */
155 // Turn on the icache, dcache, dtb translation, and itb translation.
156 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
157}
158
159void

--- 404 unchanged lines hidden --- 		155 /*
156 * T1 specific registers
157 */
158 // Turn on the icache, dcache, dtb translation, and itb translation.
159 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
160}
161
162void

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