1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#include "arch/sparc/asi.hh" 33#include "arch/sparc/handlers.hh" 34#include "arch/sparc/isa_traits.hh" 35#include "arch/sparc/registers.hh" 36#include "arch/sparc/process.hh" 37#include "arch/sparc/types.hh" 38#include "base/loader/object_file.hh" 39#include "base/loader/elf_object.hh" 40#include "base/misc.hh" 41#include "cpu/thread_context.hh" 42#include "mem/page_table.hh" 43#include "sim/process_impl.hh" 44#include "mem/translating_port.hh" 45#include "sim/system.hh" 46 47using namespace std; 48using namespace SparcISA; 49 50static const int FirstArgumentReg = 8; 51 52 53SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params, 54 ObjectFile *objFile, Addr _StackBias) 55 : LiveProcess(params, objFile), StackBias(_StackBias) 56{ 57 58 // XXX all the below need to be updated for SPARC - Ali 59 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 60 brk_point = roundUp(brk_point, VMPageSize); 61 62 // Set pointer for next thread stack. Reserve 8M for main stack. 63 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 64
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65 //Initialize these to 0s
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65 // Initialize these to 0s |
66 fillStart = 0; 67 spillStart = 0; 68} 69
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70void SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc)
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70void 71SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc) |
72{ 73 PCState pc = tc->pcState();
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73 switch(trapNum)
74 {
75 case 0x01: //Software breakpoint
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74 switch (trapNum) { 75 case 0x01: // Software breakpoint |
76 warn("Software breakpoint encountered at pc %#x.\n", pc.pc()); 77 break;
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78 case 0x02: //Division by zero
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78 case 0x02: // Division by zero |
79 warn("Software signaled a division by zero at pc %#x.\n", pc.pc()); 80 break;
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81 case 0x03: //Flush window trap
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81 case 0x03: // Flush window trap |
82 flushWindows(tc); 83 break;
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84 case 0x04: //Clean windows
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84 case 0x04: // Clean windows |
85 warn("Ignoring process request for clean register " 86 "windows at pc %#x.\n", pc.pc()); 87 break;
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88 case 0x05: //Range check
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88 case 0x05: // Range check |
89 warn("Software signaled a range check at pc %#x.\n", pc.pc()); 90 break;
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91 case 0x06: //Fix alignment
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91 case 0x06: // Fix alignment |
92 warn("Ignoring process request for os assisted unaligned accesses " 93 "at pc %#x.\n", pc.pc()); 94 break;
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95 case 0x07: //Integer overflow
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95 case 0x07: // Integer overflow |
96 warn("Software signaled an integer overflow at pc %#x.\n", pc.pc()); 97 break;
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98 case 0x32: //Get integer condition codes
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98 case 0x32: // Get integer condition codes |
99 warn("Ignoring process request to get the integer condition codes " 100 "at pc %#x.\n", pc.pc()); 101 break;
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102 case 0x33: //Set integer condition codes
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102 case 0x33: // Set integer condition codes |
103 warn("Ignoring process request to set the integer condition codes " 104 "at pc %#x.\n", pc.pc()); 105 break; 106 default: 107 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum); 108 } 109} 110 111void 112SparcLiveProcess::initState() 113{ 114 LiveProcess::initState(); 115 116 ThreadContext *tc = system->getThreadContext(contextIds[0]);
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117 //From the SPARC ABI
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117 // From the SPARC ABI |
118
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119 //Setup default FP state
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119 // Setup default FP state |
120 tc->setMiscRegNoEffect(MISCREG_FSR, 0); 121 122 tc->setMiscRegNoEffect(MISCREG_TICK, 0); 123 124 /* 125 * Register window management registers 126 */ 127
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128 //No windows contain info from other programs
129 //tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
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128 // No windows contain info from other programs 129 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0); |
130 tc->setIntReg(NumIntArchRegs + 6, 0);
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131 //There are no windows to pop
132 //tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
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131 // There are no windows to pop 132 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0); |
133 tc->setIntReg(NumIntArchRegs + 4, 0);
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134 //All windows are available to save into
135 //tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
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134 // All windows are available to save into 135 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2); |
136 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2);
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137 //All windows are "clean"
138 //tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
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137 // All windows are "clean" 138 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows); |
139 tc->setIntReg(NumIntArchRegs + 5, NWindows);
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140 //Start with register window 0
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140 // Start with register window 0 |
141 tc->setMiscReg(MISCREG_CWP, 0);
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142 //Always use spill and fill traps 0
143 //tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
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142 // Always use spill and fill traps 0 143 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0); |
144 tc->setIntReg(NumIntArchRegs + 7, 0);
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145 //Set the trap level to 0
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145 // Set the trap level to 0 |
146 tc->setMiscRegNoEffect(MISCREG_TL, 0);
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147 //Set the ASI register to something fixed
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147 // Set the ASI register to something fixed |
148 tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY); 149 150 /* 151 * T1 specific registers 152 */
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153 //Turn on the icache, dcache, dtb translation, and itb translation.
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153 // Turn on the icache, dcache, dtb translation, and itb translation. |
154 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15); 155} 156 157void 158Sparc32LiveProcess::initState() 159{ 160 SparcLiveProcess::initState(); 161 162 ThreadContext *tc = system->getThreadContext(contextIds[0]);
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163 //The process runs in user mode with 32 bit addresses
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163 // The process runs in user mode with 32 bit addresses |
164 tc->setMiscReg(MISCREG_PSTATE, 0x0a); 165 166 argsInit(32 / 8, VMPageSize); 167} 168 169void 170Sparc64LiveProcess::initState() 171{ 172 SparcLiveProcess::initState(); 173 174 ThreadContext *tc = system->getThreadContext(contextIds[0]);
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175 //The process runs in user mode
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175 // The process runs in user mode |
176 tc->setMiscReg(MISCREG_PSTATE, 0x02); 177 178 argsInit(sizeof(IntReg), VMPageSize); 179} 180 181template<class IntType> 182void 183SparcLiveProcess::argsInit(int pageSize) 184{ 185 int intSize = sizeof(IntType); 186 187 typedef AuxVector<IntType> auxv_t; 188 189 std::vector<auxv_t> auxv; 190 191 string filename;
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192 if(argv.size() < 1)
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192 if (argv.size() < 1) |
193 filename = ""; 194 else 195 filename = argv[0]; 196
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197 //Even for a 32 bit process, the ABI says we still need to
198 //maintain double word alignment of the stack pointer.
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197 // Even for a 32 bit process, the ABI says we still need to 198 // maintain double word alignment of the stack pointer. |
199 uint64_t align = 16; 200 201 // load object file into target memory 202 objFile->loadSections(initVirtMem); 203 204 enum hardwareCaps 205 { 206 M5_HWCAP_SPARC_FLUSH = 1, 207 M5_HWCAP_SPARC_STBAR = 2, 208 M5_HWCAP_SPARC_SWAP = 4, 209 M5_HWCAP_SPARC_MULDIV = 8, 210 M5_HWCAP_SPARC_V9 = 16,
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211 //This one should technically only be set
212 //if there is a cheetah or cheetah_plus tlb,
213 //but we'll use it all the time
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211 // This one should technically only be set 212 // if there is a cheetah or cheetah_plus tlb, 213 // but we'll use it all the time |
214 M5_HWCAP_SPARC_ULTRA3 = 32 215 }; 216 217 const int64_t hwcap = 218 M5_HWCAP_SPARC_FLUSH | 219 M5_HWCAP_SPARC_STBAR | 220 M5_HWCAP_SPARC_SWAP | 221 M5_HWCAP_SPARC_MULDIV | 222 M5_HWCAP_SPARC_V9 | 223 M5_HWCAP_SPARC_ULTRA3; 224
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225 //Setup the auxilliary vectors. These will already have endian conversion.
226 //Auxilliary vectors are loaded only for elf formatted executables.
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225 // Setup the auxilliary vectors. These will already have endian conversion. 226 // Auxilliary vectors are loaded only for elf formatted executables. |
227 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
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228 if(elfObject)
229 {
230 //Bits which describe the system hardware capabilities
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228 if (elfObject) { 229 // Bits which describe the system hardware capabilities |
230 auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap));
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232 //The system page size
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231 // The system page size |
232 auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize));
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234 //Defined to be 100 in the kernel source.
235 //Frequency at which times() increments
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233 // Defined to be 100 in the kernel source. 234 // Frequency at which times() increments |
235 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 236 // For statically linked executables, this is the virtual address of the 237 // program header tables if they appear in the executable image 238 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 239 // This is the size of a program header entry from the elf file. 240 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 241 // This is the number of program headers from the original elf file. 242 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
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244 //This is the address of the elf "interpreter", It should be set
245 //to 0 for regular executables. It should be something else
246 //(not sure what) for dynamic libraries.
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243 // This is the address of the elf "interpreter", It should be set 244 // to 0 for regular executables. It should be something else 245 // (not sure what) for dynamic libraries. |
246 auxv.push_back(auxv_t(M5_AT_BASE, 0));
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248 //This is hardwired to 0 in the elf loading code in the kernel
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247 // This is hardwired to 0 in the elf loading code in the kernel |
248 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
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250 //The entry point to the program
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249 // The entry point to the program |
250 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
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252 //Different user and group IDs
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251 // Different user and group IDs |
252 auxv.push_back(auxv_t(M5_AT_UID, uid())); 253 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 254 auxv.push_back(auxv_t(M5_AT_GID, gid())); 255 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
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257 //Whether to enable "secure mode" in the executable
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256 // Whether to enable "secure mode" in the executable |
257 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 258 } 259
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261 //Figure out how big the initial stack needs to be
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260 // Figure out how big the initial stack needs to be |
261 262 // The unaccounted for 8 byte 0 at the top of the stack 263 int sentry_size = 8; 264
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266 //This is the name of the file which is present on the initial stack
267 //It's purpose is to let the user space linker examine the original file.
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265 // This is the name of the file which is present on the initial stack 266 // It's purpose is to let the user space linker examine the original file. |
267 int file_name_size = filename.size() + 1; 268 269 int env_data_size = 0; 270 for (int i = 0; i < envp.size(); ++i) { 271 env_data_size += envp[i].size() + 1; 272 } 273 int arg_data_size = 0; 274 for (int i = 0; i < argv.size(); ++i) { 275 arg_data_size += argv[i].size() + 1; 276 } 277
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279 //The info_block.
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278 // The info_block. |
279 int base_info_block_size = 280 sentry_size + file_name_size + env_data_size + arg_data_size; 281 282 int info_block_size = roundUp(base_info_block_size, align); 283 284 int info_block_padding = info_block_size - base_info_block_size; 285
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287 //Each auxilliary vector is two words
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286 // Each auxilliary vector is two words |
287 int aux_array_size = intSize * 2 * (auxv.size() + 1); 288 289 int envp_array_size = intSize * (envp.size() + 1); 290 int argv_array_size = intSize * (argv.size() + 1); 291 292 int argc_size = intSize; 293 int window_save_size = intSize * 16; 294
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296 //Figure out the size of the contents of the actual initial frame
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295 // Figure out the size of the contents of the actual initial frame |
296 int frame_size = 297 aux_array_size + 298 envp_array_size + 299 argv_array_size + 300 argc_size + 301 window_save_size; 302
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304 //There needs to be padding after the auxiliary vector data so that the
305 //very bottom of the stack is aligned properly.
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303 // There needs to be padding after the auxiliary vector data so that the 304 // very bottom of the stack is aligned properly. |
305 int aligned_partial_size = roundUp(frame_size, align); 306 int aux_padding = aligned_partial_size - frame_size; 307 308 int space_needed = 309 info_block_size + 310 aux_padding + 311 frame_size; 312 313 stack_min = stack_base - space_needed; 314 stack_min = roundDown(stack_min, align); 315 stack_size = stack_base - stack_min; 316 317 // Allocate space for the stack 318 pTable->allocate(roundDown(stack_min, pageSize), 319 roundUp(stack_size, pageSize)); 320 321 // map out initial stack contents 322 IntType sentry_base = stack_base - sentry_size; 323 IntType file_name_base = sentry_base - file_name_size; 324 IntType env_data_base = file_name_base - env_data_size; 325 IntType arg_data_base = env_data_base - arg_data_size; 326 IntType auxv_array_base = arg_data_base - 327 info_block_padding - aux_array_size - aux_padding; 328 IntType envp_array_base = auxv_array_base - envp_array_size; 329 IntType argv_array_base = envp_array_base - argv_array_size; 330 IntType argc_base = argv_array_base - argc_size; 331#if TRACING_ON 332 IntType window_save_base = argc_base - window_save_size; 333#endif 334 335 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 336 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base); 337 DPRINTF(Stack, "filename = %s\n", filename); 338 DPRINTF(Stack, "%#x - file name\n", file_name_base); 339 DPRINTF(Stack, "%#x - env data\n", env_data_base); 340 DPRINTF(Stack, "%#x - arg data\n", arg_data_base); 341 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base); 342 DPRINTF(Stack, "%#x - envp array\n", envp_array_base); 343 DPRINTF(Stack, "%#x - argv array\n", argv_array_base); 344 DPRINTF(Stack, "%#x - argc \n", argc_base); 345 DPRINTF(Stack, "%#x - window save\n", window_save_base); 346 DPRINTF(Stack, "%#x - stack min\n", stack_min); 347 348 assert(window_save_base == stack_min); 349 350 // write contents to stack 351 352 // figure out argc 353 IntType argc = argv.size(); 354 IntType guestArgc = SparcISA::htog(argc); 355
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357 //Write out the sentry void *
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356 // Write out the sentry void * |
357 uint64_t sentry_NULL = 0; 358 initVirtMem->writeBlob(sentry_base, 359 (uint8_t*)&sentry_NULL, sentry_size); 360
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362 //Write the file name
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361 // Write the file name |
362 initVirtMem->writeString(file_name_base, filename.c_str()); 363
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365 //Copy the aux stuff
366 for(int x = 0; x < auxv.size(); x++)
367 {
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364 // Copy the aux stuff 365 for (int x = 0; x < auxv.size(); x++) { |
366 initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, 367 (uint8_t*)&(auxv[x].a_type), intSize); 368 initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 369 (uint8_t*)&(auxv[x].a_val), intSize); 370 } 371
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374 //Write out the terminating zeroed auxilliary vector
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372 // Write out the terminating zeroed auxilliary vector |
373 const IntType zero = 0; 374 initVirtMem->writeBlob(auxv_array_base + intSize * 2 * auxv.size(), 375 (uint8_t*)&zero, intSize); 376 initVirtMem->writeBlob(auxv_array_base + intSize * (2 * auxv.size() + 1), 377 (uint8_t*)&zero, intSize); 378 379 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 380 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 381 382 initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 383
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386 //Set up space for the trap handlers into the processes address space.
387 //Since the stack grows down and there is reserved address space abov
388 //it, we can put stuff above it and stay out of the way.
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384 // Set up space for the trap handlers into the processes address space. 385 // Since the stack grows down and there is reserved address space abov 386 // it, we can put stuff above it and stay out of the way. |
387 fillStart = stack_base; 388 spillStart = fillStart + sizeof(MachInst) * numFillInsts; 389 390 ThreadContext *tc = system->getThreadContext(contextIds[0]);
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393 //Set up the thread context to start running the process
394 //assert(NumArgumentRegs >= 2);
395 //tc->setIntReg(ArgumentReg[0], argc);
396 //tc->setIntReg(ArgumentReg[1], argv_array_base);
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391 // Set up the thread context to start running the process 392 // assert(NumArgumentRegs >= 2); 393 // tc->setIntReg(ArgumentReg[0], argc); 394 // tc->setIntReg(ArgumentReg[1], argv_array_base); |
395 tc->setIntReg(StackPointerReg, stack_min - StackBias); 396 397 // %g1 is a pointer to a function that should be run at exit. Since we 398 // don't have anything like that, it should be set to 0. 399 tc->setIntReg(1, 0); 400 401 tc->pcState(objFile->entryPoint()); 402
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405 //Align the "stack_min" to a page boundary.
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403 // Align the "stack_min" to a page boundary. |
404 stack_min = roundDown(stack_min, pageSize); 405 406// num_processes++; 407} 408 409void 410Sparc64LiveProcess::argsInit(int intSize, int pageSize) 411{ 412 SparcLiveProcess::argsInit<uint64_t>(pageSize); 413 414 // Stuff the trap handlers into the process address space 415 initVirtMem->writeBlob(fillStart, 416 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts); 417 initVirtMem->writeBlob(spillStart, 418 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts); 419} 420 421void 422Sparc32LiveProcess::argsInit(int intSize, int pageSize) 423{ 424 SparcLiveProcess::argsInit<uint32_t>(pageSize); 425 426 // Stuff the trap handlers into the process address space 427 initVirtMem->writeBlob(fillStart, 428 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts); 429 initVirtMem->writeBlob(spillStart, 430 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts); 431} 432 433void Sparc32LiveProcess::flushWindows(ThreadContext *tc) 434{ 435 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 436 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 437 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 438 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 439 MiscReg origCWP = CWP; 440 CWP = (CWP + Cansave + 2) % NWindows;
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443 while(NWindows - 2 - Cansave != 0)
444 {
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441 while (NWindows - 2 - Cansave != 0) { |
442 if (Otherwin) { 443 panic("Otherwin non-zero.\n"); 444 } else { 445 tc->setMiscReg(MISCREG_CWP, CWP);
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449 //Do the stores
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446 // Do the stores |
447 IntReg sp = tc->readIntReg(StackPointerReg); 448 for (int index = 16; index < 32; index++) { 449 uint32_t regVal = tc->readIntReg(index); 450 regVal = htog(regVal); 451 if (!tc->getMemPort()->tryWriteBlob( 452 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) { 453 warn("Failed to save register to the stack when " 454 "flushing windows.\n"); 455 } 456 } 457 Canrestore--; 458 Cansave++; 459 CWP = (CWP + 1) % NWindows; 460 } 461 } 462 tc->setIntReg(NumIntArchRegs + 3, Cansave); 463 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 464 tc->setMiscReg(MISCREG_CWP, origCWP); 465} 466
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470void Sparc64LiveProcess::flushWindows(ThreadContext *tc)
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467void 468Sparc64LiveProcess::flushWindows(ThreadContext *tc) |
469{ 470 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3); 471 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4); 472 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6); 473 MiscReg CWP = tc->readMiscReg(MISCREG_CWP); 474 MiscReg origCWP = CWP; 475 CWP = (CWP + Cansave + 2) % NWindows;
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478 while(NWindows - 2 - Cansave != 0)
479 {
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476 while (NWindows - 2 - Cansave != 0) { |
477 if (Otherwin) { 478 panic("Otherwin non-zero.\n"); 479 } else { 480 tc->setMiscReg(MISCREG_CWP, CWP);
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484 //Do the stores
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481 // Do the stores |
482 IntReg sp = tc->readIntReg(StackPointerReg); 483 for (int index = 16; index < 32; index++) { 484 IntReg regVal = tc->readIntReg(index); 485 regVal = htog(regVal); 486 if (!tc->getMemPort()->tryWriteBlob( 487 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) { 488 warn("Failed to save register to the stack when " 489 "flushing windows.\n"); 490 } 491 } 492 Canrestore--; 493 Cansave++; 494 CWP = (CWP + 1) % NWindows; 495 } 496 } 497 tc->setIntReg(NumIntArchRegs + 3, Cansave); 498 tc->setIntReg(NumIntArchRegs + 4, Canrestore); 499 tc->setMiscReg(MISCREG_CWP, origCWP); 500} 501 502IntReg 503Sparc32LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 504{ 505 assert(i < 6); 506 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 507} 508 509void 510Sparc32LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 511{ 512 assert(i < 6); 513 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 514} 515 516IntReg 517Sparc64LiveProcess::getSyscallArg(ThreadContext *tc, int &i) 518{ 519 assert(i < 6); 520 return tc->readIntReg(FirstArgumentReg + i++); 521} 522 523void 524Sparc64LiveProcess::setSyscallArg(ThreadContext *tc, int i, IntReg val) 525{ 526 assert(i < 6); 527 tc->setIntReg(FirstArgumentReg + i, val); 528} 529 530void 531SparcLiveProcess::setSyscallReturn(ThreadContext *tc, 532 SyscallReturn return_value) 533{ 534 // check for error condition. SPARC syscall convention is to 535 // indicate success/failure in reg the carry bit of the ccr 536 // and put the return value itself in the standard return value reg (). 537 if (return_value.successful()) { 538 // no error, clear XCC.C 539 tc->setIntReg(NumIntArchRegs + 2, 540 tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
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544 //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
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541 // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE); |
542 IntReg val = return_value.value(); 543 if (bits(tc->readMiscRegNoEffect( 544 SparcISA::MISCREG_PSTATE), 3, 3)) { 545 val = bits(val, 31, 0); 546 } 547 tc->setIntReg(ReturnValueReg, val); 548 } else { 549 // got an error, set XCC.C 550 tc->setIntReg(NumIntArchRegs + 2, 551 tc->readIntReg(NumIntArchRegs + 2) | 0x11);
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555 //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
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552 // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11); |
553 IntReg val = -return_value.value(); 554 if (bits(tc->readMiscRegNoEffect( 555 SparcISA::MISCREG_PSTATE), 3, 3)) { 556 val = bits(val, 31, 0); 557 } 558 tc->setIntReg(ReturnValueReg, val); 559 } 560}
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