1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34#include "arch/sparc/isa_traits.hh" 35#include "arch/sparc/process.hh" 36#include "arch/sparc/types.hh" 37#include "base/loader/object_file.hh" 38#include "base/loader/elf_object.hh" 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41#include "mem/page_table.hh" |
42#include "mem/translating_port.hh" 43#include "sim/system.hh" 44 45using namespace std; 46using namespace SparcISA; 47 48 49SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile, --- 32 unchanged lines hidden (view full) --- 82 83void 84Sparc32LiveProcess::startup() 85{ 86 argsInit(32 / 8, VMPageSize); 87 88 //From the SPARC ABI 89 |
90 //The process runs in user mode with 32 bit addresses 91 threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x0a); |
92 93 //Setup default FP state 94 threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0); 95 96 threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0); 97 // 98 /* 99 * Register window management registers --- 543 unchanged lines hidden --- |