1/* 2 * Copyright (c) 2003-2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 81 unchanged lines hidden (view full) --- 90 91 threadContexts[0]->setMiscReg(MISCREG_TICK, 0); 92 // 93 /* 94 * Register window management registers 95 */ 96 97 //No windows contain info from other programs |
98 //threadContexts[0]->setMiscReg(MISCREG_OTHERWIN, 0); 99 threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0); |
100 //There are no windows to pop |
101 //threadContexts[0]->setMiscReg(MISCREG_CANRESTORE, 0); 102 threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0); |
103 //All windows are available to save into |
104 //threadContexts[0]->setMiscReg(MISCREG_CANSAVE, NWindows - 2); 105 threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2); |
106 //All windows are "clean" |
107 //threadContexts[0]->setMiscReg(MISCREG_CLEANWIN, NWindows); 108 threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows); |
109 //Start with register window 0 110 threadContexts[0]->setMiscReg(MISCREG_CWP, 0); 111 //Always use spill and fill traps 0 |
112 //threadContexts[0]->setMiscReg(MISCREG_WSTATE, 0); 113 threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0); |
114 //Set the trap level to 0 115 threadContexts[0]->setMiscReg(MISCREG_TL, 0); 116 //Set the ASI register to something fixed 117 threadContexts[0]->setMiscReg(MISCREG_ASI, ASI_PRIMARY); 118} 119 120m5_auxv_t buildAuxVect(int64_t type, int64_t val) 121{ --- 315 unchanged lines hidden --- |