123a124,129
>
> /*
> * T1 specific registers
> */
> //Turn on the icache, dcache, dtb translation, and itb translation.
> threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
140c146
< //
---
>
165a172,177
>
> /*
> * T1 specific registers
> */
> //Turn on the icache, dcache, dtb translation, and itb translation.
> threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);