1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#include "arch/sparc/process.hh"
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/handlers.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "base/loader/elf_object.hh"
40#include "base/loader/object_file.hh"
41#include "base/logging.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Stack.hh"
44#include "mem/page_table.hh"
45#include "params/Process.hh"
46#include "sim/aux_vector.hh"
47#include "sim/process_impl.hh"
48#include "sim/syscall_return.hh"
49#include "sim/system.hh"
50
51using namespace std;
52using namespace SparcISA;
53
54static const int FirstArgumentReg = 8;
55
56
57SparcProcess::SparcProcess(ProcessParams *params, ObjectFile *objFile,
58 Addr _StackBias)
59 : Process(params,
60 new EmulationPageTable(params->name, params->pid, PageBytes),
61 objFile),
62 StackBias(_StackBias)
63{
64 fatal_if(params->useArchPT, "Arch page tables not implemented.");
65 // Initialize these to 0s
66 fillStart = 0;
67 spillStart = 0;
68}
69
70void
71SparcProcess::handleTrap(int trapNum, ThreadContext *tc, Fault *fault)
72{
73 PCState pc = tc->pcState();
74 switch (trapNum) {
75 case 0x01: // Software breakpoint
76 warn("Software breakpoint encountered at pc %#x.\n", pc.pc());
77 break;
78 case 0x02: // Division by zero
79 warn("Software signaled a division by zero at pc %#x.\n", pc.pc());
80 break;
81 case 0x03: // Flush window trap
82 flushWindows(tc);
83 break;
84 case 0x04: // Clean windows
85 warn("Ignoring process request for clean register "
86 "windows at pc %#x.\n", pc.pc());
87 break;
88 case 0x05: // Range check
89 warn("Software signaled a range check at pc %#x.\n", pc.pc());
90 break;
91 case 0x06: // Fix alignment
92 warn("Ignoring process request for os assisted unaligned accesses "
93 "at pc %#x.\n", pc.pc());
94 break;
95 case 0x07: // Integer overflow
96 warn("Software signaled an integer overflow at pc %#x.\n", pc.pc());
97 break;
98 case 0x32: // Get integer condition codes
99 warn("Ignoring process request to get the integer condition codes "
100 "at pc %#x.\n", pc.pc());
101 break;
102 case 0x33: // Set integer condition codes
103 warn("Ignoring process request to set the integer condition codes "
104 "at pc %#x.\n", pc.pc());
105 break;
106 default:
107 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
108 }
109}
110
111void
112SparcProcess::initState()
113{
114 Process::initState();
115
116 ThreadContext *tc = system->getThreadContext(contextIds[0]);
117 // From the SPARC ABI
118
119 // Setup default FP state
120 tc->setMiscRegNoEffect(MISCREG_FSR, 0);
121
122 tc->setMiscRegNoEffect(MISCREG_TICK, 0);
123
124 /*
125 * Register window management registers
126 */
127
128 // No windows contain info from other programs
129 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
130 tc->setIntReg(NumIntArchRegs + 6, 0);
131 // There are no windows to pop
132 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
133 tc->setIntReg(NumIntArchRegs + 4, 0);
134 // All windows are available to save into
135 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
136 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2);
137 // All windows are "clean"
138 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
139 tc->setIntReg(NumIntArchRegs + 5, NWindows);
140 // Start with register window 0
141 tc->setMiscReg(MISCREG_CWP, 0);
142 // Always use spill and fill traps 0
143 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
144 tc->setIntReg(NumIntArchRegs + 7, 0);
145 // Set the trap level to 0
146 tc->setMiscRegNoEffect(MISCREG_TL, 0);
147 // Set the ASI register to something fixed
148 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
149
150 // Set the MMU Primary Context Register to hold the process' pid
151 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid);
152
153 /*
154 * T1 specific registers
155 */
156 // Turn on the icache, dcache, dtb translation, and itb translation.
157 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
158}
159
160void
161Sparc32Process::initState()
162{
163 SparcProcess::initState();
164
165 ThreadContext *tc = system->getThreadContext(contextIds[0]);
166 // The process runs in user mode with 32 bit addresses
167 PSTATE pstate = 0;
168 pstate.ie = 1;
169 pstate.am = 1;
170 tc->setMiscReg(MISCREG_PSTATE, pstate);
171
172 argsInit(32 / 8, PageBytes);
173}
174
175void
176Sparc64Process::initState()
177{
178 SparcProcess::initState();
179
180 ThreadContext *tc = system->getThreadContext(contextIds[0]);
181 // The process runs in user mode
182 PSTATE pstate = 0;
183 pstate.ie = 1;
184 tc->setMiscReg(MISCREG_PSTATE, pstate);
185
186 argsInit(sizeof(RegVal), PageBytes);
187}
188
189template<class IntType>
190void
191SparcProcess::argsInit(int pageSize)
192{
193 int intSize = sizeof(IntType);
194
195 std::vector<AuxVector<IntType>> auxv;
196
197 string filename;
198 if (argv.size() < 1)
199 filename = "";
200 else
201 filename = argv[0];
202
203 // Even for a 32 bit process, the ABI says we still need to
204 // maintain double word alignment of the stack pointer.
205 uint64_t align = 16;
206
207 // Patch the ld_bias for dynamic executables.
208 updateBias();
209
210 // load object file into target memory
211 objFile->loadSections(initVirtMem);
212
213 enum hardwareCaps
214 {
215 M5_HWCAP_SPARC_FLUSH = 1,
216 M5_HWCAP_SPARC_STBAR = 2,
217 M5_HWCAP_SPARC_SWAP = 4,
218 M5_HWCAP_SPARC_MULDIV = 8,
219 M5_HWCAP_SPARC_V9 = 16,
220 // This one should technically only be set
221 // if there is a cheetah or cheetah_plus tlb,
222 // but we'll use it all the time
223 M5_HWCAP_SPARC_ULTRA3 = 32
224 };
225
226 const int64_t hwcap =
227 M5_HWCAP_SPARC_FLUSH |
228 M5_HWCAP_SPARC_STBAR |
229 M5_HWCAP_SPARC_SWAP |
230 M5_HWCAP_SPARC_MULDIV |
231 M5_HWCAP_SPARC_V9 |
232 M5_HWCAP_SPARC_ULTRA3;
233
234 // Setup the auxilliary vectors. These will already have endian conversion.
235 // Auxilliary vectors are loaded only for elf formatted executables.
236 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
237 if (elfObject) {
238 // Bits which describe the system hardware capabilities
239 auxv.emplace_back(M5_AT_HWCAP, hwcap);
240 // The system page size
241 auxv.emplace_back(M5_AT_PAGESZ, SparcISA::PageBytes);
242 // Defined to be 100 in the kernel source.
243 // Frequency at which times() increments
244 auxv.emplace_back(M5_AT_CLKTCK, 100);
245 // For statically linked executables, this is the virtual address of
246 // the program header tables if they appear in the executable image
247 auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
248 // This is the size of a program header entry from the elf file.
249 auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
250 // This is the number of program headers from the original elf file.
251 auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
252 // This is the base address of the ELF interpreter; it should be
253 // zero for static executables or contain the base address for
254 // dynamic executables.
255 auxv.emplace_back(M5_AT_BASE, getBias());
256 // This is hardwired to 0 in the elf loading code in the kernel
257 auxv.emplace_back(M5_AT_FLAGS, 0);
258 // The entry point to the program
259 auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
260 // Different user and group IDs
261 auxv.emplace_back(M5_AT_UID, uid());
262 auxv.emplace_back(M5_AT_EUID, euid());
263 auxv.emplace_back(M5_AT_GID, gid());
264 auxv.emplace_back(M5_AT_EGID, egid());
265 // Whether to enable "secure mode" in the executable
266 auxv.emplace_back(M5_AT_SECURE, 0);
267 }
268
269 // Figure out how big the initial stack needs to be
270
271 // The unaccounted for 8 byte 0 at the top of the stack
272 int sentry_size = 8;
273
274 // This is the name of the file which is present on the initial stack
275 // It's purpose is to let the user space linker examine the original file.
276 int file_name_size = filename.size() + 1;
277
278 int env_data_size = 0;
279 for (int i = 0; i < envp.size(); ++i) {
280 env_data_size += envp[i].size() + 1;
281 }
282 int arg_data_size = 0;
283 for (int i = 0; i < argv.size(); ++i) {
284 arg_data_size += argv[i].size() + 1;
285 }
286
287 // The info_block.
288 int base_info_block_size =
289 sentry_size + file_name_size + env_data_size + arg_data_size;
290
291 int info_block_size = roundUp(base_info_block_size, align);
292
293 int info_block_padding = info_block_size - base_info_block_size;
294
295 // Each auxilliary vector is two words
296 int aux_array_size = intSize * 2 * (auxv.size() + 1);
297
298 int envp_array_size = intSize * (envp.size() + 1);
299 int argv_array_size = intSize * (argv.size() + 1);
300
301 int argc_size = intSize;
302 int window_save_size = intSize * 16;
303
304 // Figure out the size of the contents of the actual initial frame
305 int frame_size =
306 aux_array_size +
307 envp_array_size +
308 argv_array_size +
309 argc_size +
310 window_save_size;
311
312 // There needs to be padding after the auxiliary vector data so that the
313 // very bottom of the stack is aligned properly.
314 int aligned_partial_size = roundUp(frame_size, align);
315 int aux_padding = aligned_partial_size - frame_size;
316
317 int space_needed =
318 info_block_size +
319 aux_padding +
320 frame_size;
321
322 memState->setStackMin(memState->getStackBase() - space_needed);
323 memState->setStackMin(roundDown(memState->getStackMin(), align));
324 memState->setStackSize(memState->getStackBase() - memState->getStackMin());
325
326 // Allocate space for the stack
327 allocateMem(roundDown(memState->getStackMin(), pageSize),
328 roundUp(memState->getStackSize(), pageSize));
329
330 // map out initial stack contents
331 IntType sentry_base = memState->getStackBase() - sentry_size;
332 IntType file_name_base = sentry_base - file_name_size;
333 IntType env_data_base = file_name_base - env_data_size;
334 IntType arg_data_base = env_data_base - arg_data_size;
335 IntType auxv_array_base = arg_data_base -
336 info_block_padding - aux_array_size - aux_padding;
337 IntType envp_array_base = auxv_array_base - envp_array_size;
338 IntType argv_array_base = envp_array_base - argv_array_size;
339 IntType argc_base = argv_array_base - argc_size;
340#if TRACING_ON
341 IntType window_save_base = argc_base - window_save_size;
342#endif
343
344 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
345 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base);
346 DPRINTF(Stack, "filename = %s\n", filename);
347 DPRINTF(Stack, "%#x - file name\n", file_name_base);
348 DPRINTF(Stack, "%#x - env data\n", env_data_base);
349 DPRINTF(Stack, "%#x - arg data\n", arg_data_base);
350 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base);
351 DPRINTF(Stack, "%#x - envp array\n", envp_array_base);
352 DPRINTF(Stack, "%#x - argv array\n", argv_array_base);
353 DPRINTF(Stack, "%#x - argc \n", argc_base);
354 DPRINTF(Stack, "%#x - window save\n", window_save_base);
355 DPRINTF(Stack, "%#x - stack min\n", memState->getStackMin());
356
357 assert(window_save_base == memState->getStackMin());
358
359 // write contents to stack
360
361 // figure out argc
362 IntType argc = argv.size();
363 IntType guestArgc = SparcISA::htog(argc);
364
365 // Write out the sentry void *
366 uint64_t sentry_NULL = 0;
| 1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#include "arch/sparc/process.hh"
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/handlers.hh"
36#include "arch/sparc/isa_traits.hh"
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "base/loader/elf_object.hh"
40#include "base/loader/object_file.hh"
41#include "base/logging.hh"
42#include "cpu/thread_context.hh"
43#include "debug/Stack.hh"
44#include "mem/page_table.hh"
45#include "params/Process.hh"
46#include "sim/aux_vector.hh"
47#include "sim/process_impl.hh"
48#include "sim/syscall_return.hh"
49#include "sim/system.hh"
50
51using namespace std;
52using namespace SparcISA;
53
54static const int FirstArgumentReg = 8;
55
56
57SparcProcess::SparcProcess(ProcessParams *params, ObjectFile *objFile,
58 Addr _StackBias)
59 : Process(params,
60 new EmulationPageTable(params->name, params->pid, PageBytes),
61 objFile),
62 StackBias(_StackBias)
63{
64 fatal_if(params->useArchPT, "Arch page tables not implemented.");
65 // Initialize these to 0s
66 fillStart = 0;
67 spillStart = 0;
68}
69
70void
71SparcProcess::handleTrap(int trapNum, ThreadContext *tc, Fault *fault)
72{
73 PCState pc = tc->pcState();
74 switch (trapNum) {
75 case 0x01: // Software breakpoint
76 warn("Software breakpoint encountered at pc %#x.\n", pc.pc());
77 break;
78 case 0x02: // Division by zero
79 warn("Software signaled a division by zero at pc %#x.\n", pc.pc());
80 break;
81 case 0x03: // Flush window trap
82 flushWindows(tc);
83 break;
84 case 0x04: // Clean windows
85 warn("Ignoring process request for clean register "
86 "windows at pc %#x.\n", pc.pc());
87 break;
88 case 0x05: // Range check
89 warn("Software signaled a range check at pc %#x.\n", pc.pc());
90 break;
91 case 0x06: // Fix alignment
92 warn("Ignoring process request for os assisted unaligned accesses "
93 "at pc %#x.\n", pc.pc());
94 break;
95 case 0x07: // Integer overflow
96 warn("Software signaled an integer overflow at pc %#x.\n", pc.pc());
97 break;
98 case 0x32: // Get integer condition codes
99 warn("Ignoring process request to get the integer condition codes "
100 "at pc %#x.\n", pc.pc());
101 break;
102 case 0x33: // Set integer condition codes
103 warn("Ignoring process request to set the integer condition codes "
104 "at pc %#x.\n", pc.pc());
105 break;
106 default:
107 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
108 }
109}
110
111void
112SparcProcess::initState()
113{
114 Process::initState();
115
116 ThreadContext *tc = system->getThreadContext(contextIds[0]);
117 // From the SPARC ABI
118
119 // Setup default FP state
120 tc->setMiscRegNoEffect(MISCREG_FSR, 0);
121
122 tc->setMiscRegNoEffect(MISCREG_TICK, 0);
123
124 /*
125 * Register window management registers
126 */
127
128 // No windows contain info from other programs
129 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
130 tc->setIntReg(NumIntArchRegs + 6, 0);
131 // There are no windows to pop
132 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
133 tc->setIntReg(NumIntArchRegs + 4, 0);
134 // All windows are available to save into
135 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
136 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2);
137 // All windows are "clean"
138 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
139 tc->setIntReg(NumIntArchRegs + 5, NWindows);
140 // Start with register window 0
141 tc->setMiscReg(MISCREG_CWP, 0);
142 // Always use spill and fill traps 0
143 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
144 tc->setIntReg(NumIntArchRegs + 7, 0);
145 // Set the trap level to 0
146 tc->setMiscRegNoEffect(MISCREG_TL, 0);
147 // Set the ASI register to something fixed
148 tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
149
150 // Set the MMU Primary Context Register to hold the process' pid
151 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, _pid);
152
153 /*
154 * T1 specific registers
155 */
156 // Turn on the icache, dcache, dtb translation, and itb translation.
157 tc->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
158}
159
160void
161Sparc32Process::initState()
162{
163 SparcProcess::initState();
164
165 ThreadContext *tc = system->getThreadContext(contextIds[0]);
166 // The process runs in user mode with 32 bit addresses
167 PSTATE pstate = 0;
168 pstate.ie = 1;
169 pstate.am = 1;
170 tc->setMiscReg(MISCREG_PSTATE, pstate);
171
172 argsInit(32 / 8, PageBytes);
173}
174
175void
176Sparc64Process::initState()
177{
178 SparcProcess::initState();
179
180 ThreadContext *tc = system->getThreadContext(contextIds[0]);
181 // The process runs in user mode
182 PSTATE pstate = 0;
183 pstate.ie = 1;
184 tc->setMiscReg(MISCREG_PSTATE, pstate);
185
186 argsInit(sizeof(RegVal), PageBytes);
187}
188
189template<class IntType>
190void
191SparcProcess::argsInit(int pageSize)
192{
193 int intSize = sizeof(IntType);
194
195 std::vector<AuxVector<IntType>> auxv;
196
197 string filename;
198 if (argv.size() < 1)
199 filename = "";
200 else
201 filename = argv[0];
202
203 // Even for a 32 bit process, the ABI says we still need to
204 // maintain double word alignment of the stack pointer.
205 uint64_t align = 16;
206
207 // Patch the ld_bias for dynamic executables.
208 updateBias();
209
210 // load object file into target memory
211 objFile->loadSections(initVirtMem);
212
213 enum hardwareCaps
214 {
215 M5_HWCAP_SPARC_FLUSH = 1,
216 M5_HWCAP_SPARC_STBAR = 2,
217 M5_HWCAP_SPARC_SWAP = 4,
218 M5_HWCAP_SPARC_MULDIV = 8,
219 M5_HWCAP_SPARC_V9 = 16,
220 // This one should technically only be set
221 // if there is a cheetah or cheetah_plus tlb,
222 // but we'll use it all the time
223 M5_HWCAP_SPARC_ULTRA3 = 32
224 };
225
226 const int64_t hwcap =
227 M5_HWCAP_SPARC_FLUSH |
228 M5_HWCAP_SPARC_STBAR |
229 M5_HWCAP_SPARC_SWAP |
230 M5_HWCAP_SPARC_MULDIV |
231 M5_HWCAP_SPARC_V9 |
232 M5_HWCAP_SPARC_ULTRA3;
233
234 // Setup the auxilliary vectors. These will already have endian conversion.
235 // Auxilliary vectors are loaded only for elf formatted executables.
236 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
237 if (elfObject) {
238 // Bits which describe the system hardware capabilities
239 auxv.emplace_back(M5_AT_HWCAP, hwcap);
240 // The system page size
241 auxv.emplace_back(M5_AT_PAGESZ, SparcISA::PageBytes);
242 // Defined to be 100 in the kernel source.
243 // Frequency at which times() increments
244 auxv.emplace_back(M5_AT_CLKTCK, 100);
245 // For statically linked executables, this is the virtual address of
246 // the program header tables if they appear in the executable image
247 auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
248 // This is the size of a program header entry from the elf file.
249 auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
250 // This is the number of program headers from the original elf file.
251 auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
252 // This is the base address of the ELF interpreter; it should be
253 // zero for static executables or contain the base address for
254 // dynamic executables.
255 auxv.emplace_back(M5_AT_BASE, getBias());
256 // This is hardwired to 0 in the elf loading code in the kernel
257 auxv.emplace_back(M5_AT_FLAGS, 0);
258 // The entry point to the program
259 auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
260 // Different user and group IDs
261 auxv.emplace_back(M5_AT_UID, uid());
262 auxv.emplace_back(M5_AT_EUID, euid());
263 auxv.emplace_back(M5_AT_GID, gid());
264 auxv.emplace_back(M5_AT_EGID, egid());
265 // Whether to enable "secure mode" in the executable
266 auxv.emplace_back(M5_AT_SECURE, 0);
267 }
268
269 // Figure out how big the initial stack needs to be
270
271 // The unaccounted for 8 byte 0 at the top of the stack
272 int sentry_size = 8;
273
274 // This is the name of the file which is present on the initial stack
275 // It's purpose is to let the user space linker examine the original file.
276 int file_name_size = filename.size() + 1;
277
278 int env_data_size = 0;
279 for (int i = 0; i < envp.size(); ++i) {
280 env_data_size += envp[i].size() + 1;
281 }
282 int arg_data_size = 0;
283 for (int i = 0; i < argv.size(); ++i) {
284 arg_data_size += argv[i].size() + 1;
285 }
286
287 // The info_block.
288 int base_info_block_size =
289 sentry_size + file_name_size + env_data_size + arg_data_size;
290
291 int info_block_size = roundUp(base_info_block_size, align);
292
293 int info_block_padding = info_block_size - base_info_block_size;
294
295 // Each auxilliary vector is two words
296 int aux_array_size = intSize * 2 * (auxv.size() + 1);
297
298 int envp_array_size = intSize * (envp.size() + 1);
299 int argv_array_size = intSize * (argv.size() + 1);
300
301 int argc_size = intSize;
302 int window_save_size = intSize * 16;
303
304 // Figure out the size of the contents of the actual initial frame
305 int frame_size =
306 aux_array_size +
307 envp_array_size +
308 argv_array_size +
309 argc_size +
310 window_save_size;
311
312 // There needs to be padding after the auxiliary vector data so that the
313 // very bottom of the stack is aligned properly.
314 int aligned_partial_size = roundUp(frame_size, align);
315 int aux_padding = aligned_partial_size - frame_size;
316
317 int space_needed =
318 info_block_size +
319 aux_padding +
320 frame_size;
321
322 memState->setStackMin(memState->getStackBase() - space_needed);
323 memState->setStackMin(roundDown(memState->getStackMin(), align));
324 memState->setStackSize(memState->getStackBase() - memState->getStackMin());
325
326 // Allocate space for the stack
327 allocateMem(roundDown(memState->getStackMin(), pageSize),
328 roundUp(memState->getStackSize(), pageSize));
329
330 // map out initial stack contents
331 IntType sentry_base = memState->getStackBase() - sentry_size;
332 IntType file_name_base = sentry_base - file_name_size;
333 IntType env_data_base = file_name_base - env_data_size;
334 IntType arg_data_base = env_data_base - arg_data_size;
335 IntType auxv_array_base = arg_data_base -
336 info_block_padding - aux_array_size - aux_padding;
337 IntType envp_array_base = auxv_array_base - envp_array_size;
338 IntType argv_array_base = envp_array_base - argv_array_size;
339 IntType argc_base = argv_array_base - argc_size;
340#if TRACING_ON
341 IntType window_save_base = argc_base - window_save_size;
342#endif
343
344 DPRINTF(Stack, "The addresses of items on the initial stack:\n");
345 DPRINTF(Stack, "%#x - sentry NULL\n", sentry_base);
346 DPRINTF(Stack, "filename = %s\n", filename);
347 DPRINTF(Stack, "%#x - file name\n", file_name_base);
348 DPRINTF(Stack, "%#x - env data\n", env_data_base);
349 DPRINTF(Stack, "%#x - arg data\n", arg_data_base);
350 DPRINTF(Stack, "%#x - auxv array\n", auxv_array_base);
351 DPRINTF(Stack, "%#x - envp array\n", envp_array_base);
352 DPRINTF(Stack, "%#x - argv array\n", argv_array_base);
353 DPRINTF(Stack, "%#x - argc \n", argc_base);
354 DPRINTF(Stack, "%#x - window save\n", window_save_base);
355 DPRINTF(Stack, "%#x - stack min\n", memState->getStackMin());
356
357 assert(window_save_base == memState->getStackMin());
358
359 // write contents to stack
360
361 // figure out argc
362 IntType argc = argv.size();
363 IntType guestArgc = SparcISA::htog(argc);
364
365 // Write out the sentry void *
366 uint64_t sentry_NULL = 0;
|
435}
436
437void Sparc32Process::flushWindows(ThreadContext *tc)
438{
439 RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
440 RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
441 RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
442 RegVal CWP = tc->readMiscReg(MISCREG_CWP);
443 RegVal origCWP = CWP;
444 CWP = (CWP + Cansave + 2) % NWindows;
445 while (NWindows - 2 - Cansave != 0) {
446 if (Otherwin) {
447 panic("Otherwin non-zero.\n");
448 } else {
449 tc->setMiscReg(MISCREG_CWP, CWP);
450 // Do the stores
451 RegVal sp = tc->readIntReg(StackPointerReg);
452 for (int index = 16; index < 32; index++) {
453 uint32_t regVal = tc->readIntReg(index);
454 regVal = htog(regVal);
455 if (!tc->getMemProxy().tryWriteBlob(
456 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) {
457 warn("Failed to save register to the stack when "
458 "flushing windows.\n");
459 }
460 }
461 Canrestore--;
462 Cansave++;
463 CWP = (CWP + 1) % NWindows;
464 }
465 }
466 tc->setIntReg(NumIntArchRegs + 3, Cansave);
467 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
468 tc->setMiscReg(MISCREG_CWP, origCWP);
469}
470
471void
472Sparc64Process::flushWindows(ThreadContext *tc)
473{
474 RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
475 RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
476 RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
477 RegVal CWP = tc->readMiscReg(MISCREG_CWP);
478 RegVal origCWP = CWP;
479 CWP = (CWP + Cansave + 2) % NWindows;
480 while (NWindows - 2 - Cansave != 0) {
481 if (Otherwin) {
482 panic("Otherwin non-zero.\n");
483 } else {
484 tc->setMiscReg(MISCREG_CWP, CWP);
485 // Do the stores
486 RegVal sp = tc->readIntReg(StackPointerReg);
487 for (int index = 16; index < 32; index++) {
488 RegVal regVal = tc->readIntReg(index);
489 regVal = htog(regVal);
490 if (!tc->getMemProxy().tryWriteBlob(
491 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) {
492 warn("Failed to save register to the stack when "
493 "flushing windows.\n");
494 }
495 }
496 Canrestore--;
497 Cansave++;
498 CWP = (CWP + 1) % NWindows;
499 }
500 }
501 tc->setIntReg(NumIntArchRegs + 3, Cansave);
502 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
503 tc->setMiscReg(MISCREG_CWP, origCWP);
504}
505
506RegVal
507Sparc32Process::getSyscallArg(ThreadContext *tc, int &i)
508{
509 assert(i < 6);
510 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0);
511}
512
513void
514Sparc32Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
515{
516 assert(i < 6);
517 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0));
518}
519
520RegVal
521Sparc64Process::getSyscallArg(ThreadContext *tc, int &i)
522{
523 assert(i < 6);
524 return tc->readIntReg(FirstArgumentReg + i++);
525}
526
527void
528Sparc64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
529{
530 assert(i < 6);
531 tc->setIntReg(FirstArgumentReg + i, val);
532}
533
534void
535SparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
536{
537 // check for error condition. SPARC syscall convention is to
538 // indicate success/failure in reg the carry bit of the ccr
539 // and put the return value itself in the standard return value reg ().
540 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
541 if (sysret.successful()) {
542 // no error, clear XCC.C
543 tc->setIntReg(NumIntArchRegs + 2,
544 tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
545 RegVal val = sysret.returnValue();
546 if (pstate.am)
547 val = bits(val, 31, 0);
548 tc->setIntReg(ReturnValueReg, val);
549 } else {
550 // got an error, set XCC.C
551 tc->setIntReg(NumIntArchRegs + 2,
552 tc->readIntReg(NumIntArchRegs + 2) | 0x11);
553 RegVal val = sysret.errnoValue();
554 if (pstate.am)
555 val = bits(val, 31, 0);
556 tc->setIntReg(ReturnValueReg, val);
557 }
558}
| 434}
435
436void Sparc32Process::flushWindows(ThreadContext *tc)
437{
438 RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
439 RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
440 RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
441 RegVal CWP = tc->readMiscReg(MISCREG_CWP);
442 RegVal origCWP = CWP;
443 CWP = (CWP + Cansave + 2) % NWindows;
444 while (NWindows - 2 - Cansave != 0) {
445 if (Otherwin) {
446 panic("Otherwin non-zero.\n");
447 } else {
448 tc->setMiscReg(MISCREG_CWP, CWP);
449 // Do the stores
450 RegVal sp = tc->readIntReg(StackPointerReg);
451 for (int index = 16; index < 32; index++) {
452 uint32_t regVal = tc->readIntReg(index);
453 regVal = htog(regVal);
454 if (!tc->getMemProxy().tryWriteBlob(
455 sp + (index - 16) * 4, (uint8_t *)®Val, 4)) {
456 warn("Failed to save register to the stack when "
457 "flushing windows.\n");
458 }
459 }
460 Canrestore--;
461 Cansave++;
462 CWP = (CWP + 1) % NWindows;
463 }
464 }
465 tc->setIntReg(NumIntArchRegs + 3, Cansave);
466 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
467 tc->setMiscReg(MISCREG_CWP, origCWP);
468}
469
470void
471Sparc64Process::flushWindows(ThreadContext *tc)
472{
473 RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
474 RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
475 RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
476 RegVal CWP = tc->readMiscReg(MISCREG_CWP);
477 RegVal origCWP = CWP;
478 CWP = (CWP + Cansave + 2) % NWindows;
479 while (NWindows - 2 - Cansave != 0) {
480 if (Otherwin) {
481 panic("Otherwin non-zero.\n");
482 } else {
483 tc->setMiscReg(MISCREG_CWP, CWP);
484 // Do the stores
485 RegVal sp = tc->readIntReg(StackPointerReg);
486 for (int index = 16; index < 32; index++) {
487 RegVal regVal = tc->readIntReg(index);
488 regVal = htog(regVal);
489 if (!tc->getMemProxy().tryWriteBlob(
490 sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) {
491 warn("Failed to save register to the stack when "
492 "flushing windows.\n");
493 }
494 }
495 Canrestore--;
496 Cansave++;
497 CWP = (CWP + 1) % NWindows;
498 }
499 }
500 tc->setIntReg(NumIntArchRegs + 3, Cansave);
501 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
502 tc->setMiscReg(MISCREG_CWP, origCWP);
503}
504
505RegVal
506Sparc32Process::getSyscallArg(ThreadContext *tc, int &i)
507{
508 assert(i < 6);
509 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0);
510}
511
512void
513Sparc32Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
514{
515 assert(i < 6);
516 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0));
517}
518
519RegVal
520Sparc64Process::getSyscallArg(ThreadContext *tc, int &i)
521{
522 assert(i < 6);
523 return tc->readIntReg(FirstArgumentReg + i++);
524}
525
526void
527Sparc64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
528{
529 assert(i < 6);
530 tc->setIntReg(FirstArgumentReg + i, val);
531}
532
533void
534SparcProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
535{
536 // check for error condition. SPARC syscall convention is to
537 // indicate success/failure in reg the carry bit of the ccr
538 // and put the return value itself in the standard return value reg ().
539 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
540 if (sysret.successful()) {
541 // no error, clear XCC.C
542 tc->setIntReg(NumIntArchRegs + 2,
543 tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
544 RegVal val = sysret.returnValue();
545 if (pstate.am)
546 val = bits(val, 31, 0);
547 tc->setIntReg(ReturnValueReg, val);
548 } else {
549 // got an error, set XCC.C
550 tc->setIntReg(NumIntArchRegs + 2,
551 tc->readIntReg(NumIntArchRegs + 2) | 0x11);
552 RegVal val = sysret.errnoValue();
553 if (pstate.am)
554 val = bits(val, 31, 0);
555 tc->setIntReg(ReturnValueReg, val);
556 }
557}
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