1/*
2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#include "arch/sparc/asi.hh"
33#include "arch/sparc/handlers.hh"
34#include "arch/sparc/isa_traits.hh"
35#include "arch/sparc/process.hh"
36#include "arch/sparc/types.hh"
37#include "base/loader/object_file.hh"
38#include "base/loader/elf_object.hh"
39#include "base/misc.hh"
40#include "cpu/thread_context.hh"
41#include "mem/page_table.hh"
42#include "sim/process_impl.hh"
43#include "mem/translating_port.hh"
44#include "sim/system.hh"
45
46using namespace std;
47using namespace SparcISA;
48
49
50SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params,
51 ObjectFile *objFile, Addr _StackBias)
52 : LiveProcess(params, objFile), StackBias(_StackBias)
53{
54
55 // XXX all the below need to be updated for SPARC - Ali
56 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
57 brk_point = roundUp(brk_point, VMPageSize);
58
59 // Set pointer for next thread stack. Reserve 8M for main stack.
60 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
61
62 //Initialize these to 0s
63 fillStart = 0;
64 spillStart = 0;
65}
66
67void SparcLiveProcess::handleTrap(int trapNum, ThreadContext *tc)
68{
69 switch(trapNum)
70 {
71 case 0x01: //Software breakpoint
72 warn("Software breakpoint encountered at pc %#x.\n", tc->readPC());
73 break;
74 case 0x02: //Division by zero
75 warn("Software signaled a division by zero at pc %#x.\n",
76 tc->readPC());
77 break;
78 case 0x03: //Flush window trap
79 flushWindows(tc);
80 break;
81 case 0x04: //Clean windows
82 warn("Ignoring process request for clean register "
83 "windows at pc %#x.\n", tc->readPC());
84 break;
85 case 0x05: //Range check
86 warn("Software signaled a range check at pc %#x.\n",
87 tc->readPC());
88 break;
89 case 0x06: //Fix alignment
90 warn("Ignoring process request for os assisted unaligned accesses "
91 "at pc %#x.\n", tc->readPC());
92 break;
93 case 0x07: //Integer overflow
94 warn("Software signaled an integer overflow at pc %#x.\n",
95 tc->readPC());
96 break;
97 case 0x32: //Get integer condition codes
98 warn("Ignoring process request to get the integer condition codes "
99 "at pc %#x.\n", tc->readPC());
100 break;
101 case 0x33: //Set integer condition codes
102 warn("Ignoring process request to set the integer condition codes "
103 "at pc %#x.\n", tc->readPC());
104 break;
105 default:
106 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
107 }
108}
109
110void
111SparcLiveProcess::startup()
112{
113 Process::startup();
114
115 //From the SPARC ABI
116
117 //Setup default FP state
118 threadContexts[0]->setMiscRegNoEffect(MISCREG_FSR, 0);
119
120 threadContexts[0]->setMiscRegNoEffect(MISCREG_TICK, 0);
121
122 /*
123 * Register window management registers
124 */
125
126 //No windows contain info from other programs
127 //threadContexts[0]->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
128 threadContexts[0]->setIntReg(NumIntArchRegs + 6, 0);
129 //There are no windows to pop
130 //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
131 threadContexts[0]->setIntReg(NumIntArchRegs + 4, 0);
132 //All windows are available to save into
133 //threadContexts[0]->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
134 threadContexts[0]->setIntReg(NumIntArchRegs + 3, NWindows - 2);
135 //All windows are "clean"
136 //threadContexts[0]->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
137 threadContexts[0]->setIntReg(NumIntArchRegs + 5, NWindows);
138 //Start with register window 0
139 threadContexts[0]->setMiscRegNoEffect(MISCREG_CWP, 0);
140 //Always use spill and fill traps 0
141 //threadContexts[0]->setMiscRegNoEffect(MISCREG_WSTATE, 0);
142 threadContexts[0]->setIntReg(NumIntArchRegs + 7, 0);
143 //Set the trap level to 0
144 threadContexts[0]->setMiscRegNoEffect(MISCREG_TL, 0);
145 //Set the ASI register to something fixed
146 threadContexts[0]->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
147
148 /*
149 * T1 specific registers
150 */
151 //Turn on the icache, dcache, dtb translation, and itb translation.
152 threadContexts[0]->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL, 15);
153}
154
155void
156Sparc32LiveProcess::startup()
157{
158 if (checkpointRestored)
159 return;
160
161 SparcLiveProcess::startup();
162
163 //The process runs in user mode with 32 bit addresses
164 threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x0a);
165
166 argsInit(32 / 8, VMPageSize);
167}
168
169void
170Sparc64LiveProcess::startup()
171{
172 if (checkpointRestored)
173 return;
174
175 SparcLiveProcess::startup();
176
177 //The process runs in user mode
178 threadContexts[0]->setMiscReg(MISCREG_PSTATE, 0x02);
179
180 argsInit(sizeof(IntReg), VMPageSize);
181}
182
183template<class IntType>
184void
185SparcLiveProcess::argsInit(int pageSize)
186{
187 int intSize = sizeof(IntType);
188
189 typedef M5_auxv_t<IntType> auxv_t;
190
191 std::vector<auxv_t> auxv;
192
193 string filename;
194 if(argv.size() < 1)
195 filename = "";
196 else
197 filename = argv[0];
198
199 //Even for a 32 bit process, the ABI says we still need to
200 //maintain double word alignment of the stack pointer.
201 Addr alignmentMask = ~(sizeof(uint64_t) - 1);
202
203 // load object file into target memory
204 objFile->loadSections(initVirtMem);
205
206 enum hardwareCaps
207 {
208 M5_HWCAP_SPARC_FLUSH = 1,
209 M5_HWCAP_SPARC_STBAR = 2,
210 M5_HWCAP_SPARC_SWAP = 4,
211 M5_HWCAP_SPARC_MULDIV = 8,
212 M5_HWCAP_SPARC_V9 = 16,
213 //This one should technically only be set
214 //if there is a cheetah or cheetah_plus tlb,
215 //but we'll use it all the time
216 M5_HWCAP_SPARC_ULTRA3 = 32
217 };
218
219 const int64_t hwcap =
220 M5_HWCAP_SPARC_FLUSH |
221 M5_HWCAP_SPARC_STBAR |
222 M5_HWCAP_SPARC_SWAP |
223 M5_HWCAP_SPARC_MULDIV |
224 M5_HWCAP_SPARC_V9 |
225 M5_HWCAP_SPARC_ULTRA3;
226
227 //Setup the auxilliary vectors. These will already have endian conversion.
228 //Auxilliary vectors are loaded only for elf formatted executables.
229 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
230 if(elfObject)
231 {
232 //Bits which describe the system hardware capabilities
233 auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap));
234 //The system page size
235 auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize));
236 //Defined to be 100 in the kernel source.
237 //Frequency at which times() increments
238 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
239 // For statically linked executables, this is the virtual address of the
240 // program header tables if they appear in the executable image
241 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
242 // This is the size of a program header entry from the elf file.
243 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
244 // This is the number of program headers from the original elf file.
245 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
246 //This is the address of the elf "interpreter", It should be set
247 //to 0 for regular executables. It should be something else
248 //(not sure what) for dynamic libraries.
249 auxv.push_back(auxv_t(M5_AT_BASE, 0));
250 //This is hardwired to 0 in the elf loading code in the kernel
251 auxv.push_back(auxv_t(M5_AT_FLAGS, 0));
252 //The entry point to the program
253 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
254 //Different user and group IDs
255 auxv.push_back(auxv_t(M5_AT_UID, uid()));
256 auxv.push_back(auxv_t(M5_AT_EUID, euid()));
257 auxv.push_back(auxv_t(M5_AT_GID, gid()));
258 auxv.push_back(auxv_t(M5_AT_EGID, egid()));
259 //Whether to enable "secure mode" in the executable
260 auxv.push_back(auxv_t(M5_AT_SECURE, 0));
261 }
262
263 //Figure out how big the initial stack needs to be
264
265 // The unaccounted for 8 byte 0 at the top of the stack
266 int mysterious_size = 8;
267
268 //This is the name of the file which is present on the initial stack
269 //It's purpose is to let the user space linker examine the original file.
270 int file_name_size = filename.size() + 1;
271
272 int env_data_size = 0;
273 for (int i = 0; i < envp.size(); ++i) {
274 env_data_size += envp[i].size() + 1;
275 }
276 int arg_data_size = 0;
277 for (int i = 0; i < argv.size(); ++i) {
278 arg_data_size += argv[i].size() + 1;
279 }
280
281 //The info_block - This seems to need an pad for some reason.
282 int info_block_size =
283 (mysterious_size +
284 file_name_size +
285 env_data_size +
286 arg_data_size + intSize);
287
288 //Each auxilliary vector is two words
289 int aux_array_size = intSize * 2 * (auxv.size() + 1);
290
291 int envp_array_size = intSize * (envp.size() + 1);
292 int argv_array_size = intSize * (argv.size() + 1);
293
294 int argc_size = intSize;
295 int window_save_size = intSize * 16;
296
297 int space_needed =
298 info_block_size +
299 aux_array_size +
300 envp_array_size +
301 argv_array_size +
302 argc_size +
303 window_save_size;
304
305 stack_min = stack_base - space_needed;
306 stack_min &= alignmentMask;
307 stack_size = stack_base - stack_min;
308
309 // Allocate space for the stack
310 pTable->allocate(roundDown(stack_min, pageSize),
311 roundUp(stack_size, pageSize));
312
313 // map out initial stack contents
314 IntType window_save_base = stack_min;
315 IntType argc_base = window_save_base + window_save_size;
316 IntType argv_array_base = argc_base + argc_size;
317 IntType envp_array_base = argv_array_base + argv_array_size;
318 IntType auxv_array_base = envp_array_base + envp_array_size;
319 //The info block is pushed up against the top of the stack, while
320 //the rest of the initial stack frame is aligned to an 8 byte boudary.
321 IntType arg_data_base = stack_base - info_block_size + intSize;
322 IntType env_data_base = arg_data_base + arg_data_size;
323 IntType file_name_base = env_data_base + env_data_size;
324 IntType mysterious_base = file_name_base + file_name_size;
325
326 DPRINTF(Sparc, "The addresses of items on the initial stack:\n");
327 DPRINTF(Sparc, "%#x - file name\n", file_name_base);
328 DPRINTF(Sparc, "%#x - env data\n", env_data_base);
329 DPRINTF(Sparc, "%#x - arg data\n", arg_data_base);
330 DPRINTF(Sparc, "%#x - auxv array\n", auxv_array_base);
331 DPRINTF(Sparc, "%#x - envp array\n", envp_array_base);
332 DPRINTF(Sparc, "%#x - argv array\n", argv_array_base);
333 DPRINTF(Sparc, "%#x - argc \n", argc_base);
334 DPRINTF(Sparc, "%#x - window save\n", window_save_base);
335 DPRINTF(Sparc, "%#x - stack min\n", stack_min);
336
337 // write contents to stack
338
339 // figure out argc
340 IntType argc = argv.size();
341 IntType guestArgc = TheISA::htog(argc);
342
343 //Write out the mysterious 0
344 uint64_t mysterious_zero = 0;
345 initVirtMem->writeBlob(mysterious_base,
346 (uint8_t*)&mysterious_zero, mysterious_size);
347
348 //Write the file name
349 initVirtMem->writeString(file_name_base, filename.c_str());
350
351 //Copy the aux stuff
352 for(int x = 0; x < auxv.size(); x++)
353 {
354 initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
355 (uint8_t*)&(auxv[x].a_type), intSize);
356 initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
357 (uint8_t*)&(auxv[x].a_val), intSize);
358 }
359
360 //Write out the terminating zeroed auxilliary vector
361 const IntType zero = 0;
362 initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
363 (uint8_t*)&zero, 2 * intSize);
364
365 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
366 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
367
368 initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
369
370 //Set up space for the trap handlers into the processes address space.
371 //Since the stack grows down and there is reserved address space abov
372 //it, we can put stuff above it and stay out of the way.
373 fillStart = stack_base;
374 spillStart = fillStart + sizeof(MachInst) * numFillInsts;
375
376 //Set up the thread context to start running the process
377 //assert(NumArgumentRegs >= 2);
378 //threadContexts[0]->setIntReg(ArgumentReg[0], argc);
379 //threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
380 threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
381
382 // %g1 is a pointer to a function that should be run at exit. Since we
383 // don't have anything like that, it should be set to 0.
384 threadContexts[0]->setIntReg(1, 0);
385
386 Addr prog_entry = objFile->entryPoint();
387 threadContexts[0]->setPC(prog_entry);
388 threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
389 threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
390
391 //Align the "stack_min" to a page boundary.
392 stack_min = roundDown(stack_min, pageSize);
393
394// num_processes++;
395}
396
397void
398Sparc64LiveProcess::argsInit(int intSize, int pageSize)
399{
400 SparcLiveProcess::argsInit<uint64_t>(pageSize);
401
402 // Stuff the trap handlers into the process address space
403 initVirtMem->writeBlob(fillStart,
404 (uint8_t*)fillHandler64, sizeof(MachInst) * numFillInsts);
405 initVirtMem->writeBlob(spillStart,
406 (uint8_t*)spillHandler64, sizeof(MachInst) * numSpillInsts);
407}
408
409void
410Sparc32LiveProcess::argsInit(int intSize, int pageSize)
411{
412 SparcLiveProcess::argsInit<uint32_t>(pageSize);
413
414 // Stuff the trap handlers into the process address space
415 initVirtMem->writeBlob(fillStart,
416 (uint8_t*)fillHandler32, sizeof(MachInst) * numFillInsts);
417 initVirtMem->writeBlob(spillStart,
418 (uint8_t*)spillHandler32, sizeof(MachInst) * numSpillInsts);
419}
420
421void Sparc32LiveProcess::flushWindows(ThreadContext *tc)
422{
423 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
424 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
425 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
426 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
427 MiscReg origCWP = CWP;
428 CWP = (CWP + Cansave + 2) % NWindows;
429 while(NWindows - 2 - Cansave != 0)
430 {
431 if (Otherwin) {
432 panic("Otherwin non-zero.\n");
433 } else {
434 tc->setMiscReg(MISCREG_CWP, CWP);
435 //Do the stores
436 IntReg sp = tc->readIntReg(StackPointerReg);
437 for (int index = 16; index < 32; index++) {
438 IntReg regVal = tc->readIntReg(index);
439 regVal = htog(regVal);
440 if (!tc->getMemPort()->tryWriteBlob(
441 sp + (index - 16) * 4, (uint8_t *)&regVal, 4)) {
442 warn("Failed to save register to the stack when "
443 "flushing windows.\n");
444 }
445 }
446 Canrestore--;
447 Cansave++;
448 CWP = (CWP + 1) % NWindows;
449 }
450 }
451 tc->setIntReg(NumIntArchRegs + 3, Cansave);
452 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
453 tc->setMiscReg(MISCREG_CWP, origCWP);
454}
455
456void Sparc64LiveProcess::flushWindows(ThreadContext *tc)
457{
458 IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
459 IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
460 IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
461 MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
462 MiscReg origCWP = CWP;
463 CWP = (CWP + Cansave + 2) % NWindows;
464 while(NWindows - 2 - Cansave != 0)
465 {
466 if (Otherwin) {
467 panic("Otherwin non-zero.\n");
468 } else {
469 tc->setMiscReg(MISCREG_CWP, CWP);
470 //Do the stores
471 IntReg sp = tc->readIntReg(StackPointerReg);
472 for (int index = 16; index < 32; index++) {
473 IntReg regVal = tc->readIntReg(index);
474 regVal = htog(regVal);
475 if (!tc->getMemPort()->tryWriteBlob(
476 sp + 2047 + (index - 16) * 8, (uint8_t *)&regVal, 8)) {
477 warn("Failed to save register to the stack when "
478 "flushing windows.\n");
479 }
480 }
481 Canrestore--;
482 Cansave++;
483 CWP = (CWP + 1) % NWindows;
484 }
485 }
486 tc->setIntReg(NumIntArchRegs + 3, Cansave);
487 tc->setIntReg(NumIntArchRegs + 4, Canrestore);
488 tc->setMiscReg(MISCREG_CWP, origCWP);
489}