pagetable.hh (8794:e2ac2b7164dd) pagetable.hh (10558:426665ec11a9)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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225};
226
227
228struct TlbEntry
229{
230 TlbEntry()
231 {}
232
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 216 unchanged lines hidden (view full) ---

225};
226
227
228struct TlbEntry
229{
230 TlbEntry()
231 {}
232
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr)
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr,
234 bool uncacheable, bool read_only)
234 {
235 uint64_t entry = 0;
235 {
236 uint64_t entry = 0;
236 entry |= 1ULL << 1; // Writable
237 if (!read_only)
238 entry |= 1ULL << 1; // Writable
237 entry |= 0ULL << 2; // Available in nonpriveleged mode
238 entry |= 0ULL << 3; // No side effects
239 entry |= 0ULL << 2; // Available in nonpriveleged mode
240 entry |= 0ULL << 3; // No side effects
239 entry |= 1ULL << 4; // Virtually cachable
240 entry |= 1ULL << 5; // Physically cachable
241 if (!uncacheable) {
242 entry |= 1ULL << 4; // Virtually cachable
243 entry |= 1ULL << 5; // Physically cachable
244 }
241 entry |= 0ULL << 6; // Not locked
242 entry |= mbits(paddr, 39, 13); // Physical address
243 entry |= 0ULL << 48; // size = 8k
244 entry |= 0uLL << 59; // Endianness not inverted
245 entry |= 0ULL << 60; // Not no fault only
246 entry |= 0ULL << 61; // size = 8k
247 entry |= 1ULL << 63; // valid
248 pte = PageTableEntry(entry);

--- 35 unchanged lines hidden --- 		245 entry |= 0ULL << 6; // Not locked
246 entry |= mbits(paddr, 39, 13); // Physical address
247 entry |= 0ULL << 48; // size = 8k
248 entry |= 0uLL << 59; // Endianness not inverted
249 entry |= 0ULL << 60; // Not no fault only
250 entry |= 0ULL << 61; // size = 8k
251 entry |= 1ULL << 63; // valid
252 pte = PageTableEntry(entry);

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