1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_PAGETABLE_HH__
32#define __ARCH_SPARC_PAGETABLE_HH__
33
34#include <cassert>
35
36#include "arch/sparc/isa_traits.hh"
37#include "base/bitfield.hh"
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_PAGETABLE_HH__
32#define __ARCH_SPARC_PAGETABLE_HH__
33
34#include <cassert>
35
36#include "arch/sparc/isa_traits.hh"
37#include "base/bitfield.hh"
|
39
40class Checkpoint;
41
42namespace SparcISA {
43
44struct VAddr
45{
46 VAddr(Addr a) { panic("not implemented yet."); }
47};
48
49class TteTag
50{
51 private:
52 uint64_t entry;
53 bool populated;
54
55 public:
56 TteTag() : entry(0), populated(false) {}
57 TteTag(uint64_t e) : entry(e), populated(true) {}
58
59 const TteTag &
60 operator=(uint64_t e)
61 {
62 populated = true;
63 entry = e;
64 return *this;
65 }
66
67 bool valid() const { assert(populated); return !bits(entry,62,62); }
68 Addr va() const { assert(populated); return bits(entry,41,0); }
69};
70
71
72class PageTableEntry
73{
74 public:
75 enum EntryType {
76 sun4v,
77 sun4u,
78 invalid
79 };
80
81 private:
82 uint64_t entry;
83 EntryType type;
84 uint64_t entry4u;
85 bool populated;
86
87 public:
88 PageTableEntry() : entry(0), type(invalid), populated(false)
89 {}
90
91 PageTableEntry(uint64_t e, EntryType t = sun4u)
92 : entry(e), type(t), populated(true)
93 {
94 populate(entry, type);
95 }
96
97 void
98 populate(uint64_t e, EntryType t = sun4u)
99 {
100 entry = e;
101 type = t;
102 populated = true;
103
104 // If we get a sun4v format TTE, turn it into a sun4u
105 if (type == sun4u)
106 entry4u = entry;
107 else {
108 entry4u = 0;
109 entry4u |= mbits(entry,63,63); // valid
110 entry4u |= bits(entry,1,0) << 61; // size[1:0]
111 entry4u |= bits(entry,62,62) << 60; // nfo
112 entry4u |= bits(entry,12,12) << 59; // ie
113 entry4u |= bits(entry,2,2) << 48; // size[2]
114 entry4u |= mbits(entry,39,13); // paddr
115 entry4u |= bits(entry,61,61) << 6;; // locked
116 entry4u |= bits(entry,10,10) << 5; // cp
117 entry4u |= bits(entry,9,9) << 4; // cv
118 entry4u |= bits(entry,11,11) << 3; // e
119 entry4u |= bits(entry,8,8) << 2; // p
120 entry4u |= bits(entry,6,6) << 1; // w
121 }
122 }
123
124 void
125 clear()
126 {
127 populated = false;
128 }
129
130 static int pageSizes[6];
131
132 uint64_t operator()() const { assert(populated); return entry4u; }
133
134 const PageTableEntry &
135 operator=(uint64_t e)
136 {
137 populated = true;
138 entry4u = e;
139 return *this;
140 }
141
142 const PageTableEntry &
143 operator=(const PageTableEntry &e)
144 {
145 populated = true;
146 entry4u = e.entry4u;
147 type = e.type;
148 return *this;
149 }
150
151 bool valid() const { return bits(entry4u,63,63) && populated; }
152
153 uint8_t
154 _size() const
155 {
156 assert(populated);
157 return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
158 }
159
160 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
161 Addr sizeMask() const { return size() - 1; }
162 bool ie() const { return bits(entry4u, 59,59); }
163 Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
164 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
165 bool locked() const { assert(populated); return bits(entry4u,6,6); }
166 bool cv() const { assert(populated); return bits(entry4u,4,4); }
167 bool cp() const { assert(populated); return bits(entry4u,5,5); }
168 bool priv() const { assert(populated); return bits(entry4u,2,2); }
169 bool writable() const { assert(populated); return bits(entry4u,1,1); }
170 bool nofault() const { assert(populated); return bits(entry4u,60,60); }
171 bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
172 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
173
174 Addr
175 translate(Addr vaddr) const
176 {
177 assert(populated);
178 Addr mask = sizeMask();
179 return (paddr() & ~mask) | (vaddr & mask);
180 }
181};
182
183struct TlbRange
184{
185 Addr va;
186 Addr size;
187 int contextId;
188 int partitionId;
189 bool real;
190
191 inline bool
192 operator<(const TlbRange &r2) const
193 {
194 if (real && !r2.real)
195 return true;
196 if (!real && r2.real)
197 return false;
198
199 if (!real && !r2.real) {
200 if (contextId < r2.contextId)
201 return true;
202 else if (contextId > r2.contextId)
203 return false;
204 }
205
206 if (partitionId < r2.partitionId)
207 return true;
208 else if (partitionId > r2.partitionId)
209 return false;
210
211 if (va < r2.va)
212 return true;
213 return false;
214 }
215
216 inline bool
217 operator==(const TlbRange &r2) const
218 {
219 return va == r2.va &&
220 size == r2.size &&
221 contextId == r2.contextId &&
222 partitionId == r2.partitionId &&
223 real == r2.real;
224 }
225};
226
227
228struct TlbEntry
229{
230 TlbEntry()
231 {}
232
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr,
234 bool uncacheable, bool read_only)
235 {
236 uint64_t entry = 0;
237 if (!read_only)
238 entry |= 1ULL << 1; // Writable
239 entry |= 0ULL << 2; // Available in nonpriveleged mode
240 entry |= 0ULL << 3; // No side effects
241 if (!uncacheable) {
242 entry |= 1ULL << 4; // Virtually cachable
243 entry |= 1ULL << 5; // Physically cachable
244 }
245 entry |= 0ULL << 6; // Not locked
246 entry |= mbits(paddr, 39, 13); // Physical address
247 entry |= 0ULL << 48; // size = 8k
248 entry |= 0uLL << 59; // Endianness not inverted
249 entry |= 0ULL << 60; // Not no fault only
250 entry |= 0ULL << 61; // size = 8k
251 entry |= 1ULL << 63; // valid
252 pte = PageTableEntry(entry);
253
254 range.va = vaddr;
255 range.size = 8*(1<<10);
256 range.contextId = asn;
257 range.partitionId = 0;
258 range.real = false;
259
260 valid = true;
261 }
262
263 TlbRange range;
264 PageTableEntry pte;
265 bool used;
266 bool valid;
267
268 Addr
269 pageStart()
270 {
271 return pte.paddr();
272 }
273
274 void
275 updateVaddr(Addr new_vaddr)
276 {
277 range.va = new_vaddr;
278 }
279
280 void serialize(CheckpointOut &cp) const;
281 void unserialize(CheckpointIn &cp);
282};
283
284} // namespace SparcISA
285
286#endif // __ARCH_SPARC_PAGE_TABLE_HH__
287
| 39
40class Checkpoint;
41
42namespace SparcISA {
43
44struct VAddr
45{
46 VAddr(Addr a) { panic("not implemented yet."); }
47};
48
49class TteTag
50{
51 private:
52 uint64_t entry;
53 bool populated;
54
55 public:
56 TteTag() : entry(0), populated(false) {}
57 TteTag(uint64_t e) : entry(e), populated(true) {}
58
59 const TteTag &
60 operator=(uint64_t e)
61 {
62 populated = true;
63 entry = e;
64 return *this;
65 }
66
67 bool valid() const { assert(populated); return !bits(entry,62,62); }
68 Addr va() const { assert(populated); return bits(entry,41,0); }
69};
70
71
72class PageTableEntry
73{
74 public:
75 enum EntryType {
76 sun4v,
77 sun4u,
78 invalid
79 };
80
81 private:
82 uint64_t entry;
83 EntryType type;
84 uint64_t entry4u;
85 bool populated;
86
87 public:
88 PageTableEntry() : entry(0), type(invalid), populated(false)
89 {}
90
91 PageTableEntry(uint64_t e, EntryType t = sun4u)
92 : entry(e), type(t), populated(true)
93 {
94 populate(entry, type);
95 }
96
97 void
98 populate(uint64_t e, EntryType t = sun4u)
99 {
100 entry = e;
101 type = t;
102 populated = true;
103
104 // If we get a sun4v format TTE, turn it into a sun4u
105 if (type == sun4u)
106 entry4u = entry;
107 else {
108 entry4u = 0;
109 entry4u |= mbits(entry,63,63); // valid
110 entry4u |= bits(entry,1,0) << 61; // size[1:0]
111 entry4u |= bits(entry,62,62) << 60; // nfo
112 entry4u |= bits(entry,12,12) << 59; // ie
113 entry4u |= bits(entry,2,2) << 48; // size[2]
114 entry4u |= mbits(entry,39,13); // paddr
115 entry4u |= bits(entry,61,61) << 6;; // locked
116 entry4u |= bits(entry,10,10) << 5; // cp
117 entry4u |= bits(entry,9,9) << 4; // cv
118 entry4u |= bits(entry,11,11) << 3; // e
119 entry4u |= bits(entry,8,8) << 2; // p
120 entry4u |= bits(entry,6,6) << 1; // w
121 }
122 }
123
124 void
125 clear()
126 {
127 populated = false;
128 }
129
130 static int pageSizes[6];
131
132 uint64_t operator()() const { assert(populated); return entry4u; }
133
134 const PageTableEntry &
135 operator=(uint64_t e)
136 {
137 populated = true;
138 entry4u = e;
139 return *this;
140 }
141
142 const PageTableEntry &
143 operator=(const PageTableEntry &e)
144 {
145 populated = true;
146 entry4u = e.entry4u;
147 type = e.type;
148 return *this;
149 }
150
151 bool valid() const { return bits(entry4u,63,63) && populated; }
152
153 uint8_t
154 _size() const
155 {
156 assert(populated);
157 return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
158 }
159
160 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
161 Addr sizeMask() const { return size() - 1; }
162 bool ie() const { return bits(entry4u, 59,59); }
163 Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
164 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
165 bool locked() const { assert(populated); return bits(entry4u,6,6); }
166 bool cv() const { assert(populated); return bits(entry4u,4,4); }
167 bool cp() const { assert(populated); return bits(entry4u,5,5); }
168 bool priv() const { assert(populated); return bits(entry4u,2,2); }
169 bool writable() const { assert(populated); return bits(entry4u,1,1); }
170 bool nofault() const { assert(populated); return bits(entry4u,60,60); }
171 bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
172 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
173
174 Addr
175 translate(Addr vaddr) const
176 {
177 assert(populated);
178 Addr mask = sizeMask();
179 return (paddr() & ~mask) | (vaddr & mask);
180 }
181};
182
183struct TlbRange
184{
185 Addr va;
186 Addr size;
187 int contextId;
188 int partitionId;
189 bool real;
190
191 inline bool
192 operator<(const TlbRange &r2) const
193 {
194 if (real && !r2.real)
195 return true;
196 if (!real && r2.real)
197 return false;
198
199 if (!real && !r2.real) {
200 if (contextId < r2.contextId)
201 return true;
202 else if (contextId > r2.contextId)
203 return false;
204 }
205
206 if (partitionId < r2.partitionId)
207 return true;
208 else if (partitionId > r2.partitionId)
209 return false;
210
211 if (va < r2.va)
212 return true;
213 return false;
214 }
215
216 inline bool
217 operator==(const TlbRange &r2) const
218 {
219 return va == r2.va &&
220 size == r2.size &&
221 contextId == r2.contextId &&
222 partitionId == r2.partitionId &&
223 real == r2.real;
224 }
225};
226
227
228struct TlbEntry
229{
230 TlbEntry()
231 {}
232
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr,
234 bool uncacheable, bool read_only)
235 {
236 uint64_t entry = 0;
237 if (!read_only)
238 entry |= 1ULL << 1; // Writable
239 entry |= 0ULL << 2; // Available in nonpriveleged mode
240 entry |= 0ULL << 3; // No side effects
241 if (!uncacheable) {
242 entry |= 1ULL << 4; // Virtually cachable
243 entry |= 1ULL << 5; // Physically cachable
244 }
245 entry |= 0ULL << 6; // Not locked
246 entry |= mbits(paddr, 39, 13); // Physical address
247 entry |= 0ULL << 48; // size = 8k
248 entry |= 0uLL << 59; // Endianness not inverted
249 entry |= 0ULL << 60; // Not no fault only
250 entry |= 0ULL << 61; // size = 8k
251 entry |= 1ULL << 63; // valid
252 pte = PageTableEntry(entry);
253
254 range.va = vaddr;
255 range.size = 8*(1<<10);
256 range.contextId = asn;
257 range.partitionId = 0;
258 range.real = false;
259
260 valid = true;
261 }
262
263 TlbRange range;
264 PageTableEntry pte;
265 bool used;
266 bool valid;
267
268 Addr
269 pageStart()
270 {
271 return pte.paddr();
272 }
273
274 void
275 updateVaddr(Addr new_vaddr)
276 {
277 range.va = new_vaddr;
278 }
279
280 void serialize(CheckpointOut &cp) const;
281 void unserialize(CheckpointIn &cp);
282};
283
284} // namespace SparcISA
285
286#endif // __ARCH_SPARC_PAGE_TABLE_HH__
287
|