miscregs.hh (7741:340b6f01d69b) miscregs.hh (8829:d21889bface6)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_MISCREGS_HH__
33#define __ARCH_SPARC_MISCREGS_HH__
34
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_MISCREGS_HH__
33#define __ARCH_SPARC_MISCREGS_HH__
34
35#include "base/bitunion.hh"
35#include "base/types.hh"
36
37namespace SparcISA
38{
39enum MiscRegIndex
40{
41 /** Ancillary State Registers */
42// MISCREG_Y,

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110 MISCREG_QUEUE_NRES_ERROR_HEAD,
111 MISCREG_QUEUE_NRES_ERROR_TAIL,
112
113 /* All the data for the TLB packed up in one register. */
114 MISCREG_TLB_DATA,
115 MISCREG_NUMMISCREGS
116};
117
36#include "base/types.hh"
37
38namespace SparcISA
39{
40enum MiscRegIndex
41{
42 /** Ancillary State Registers */
43// MISCREG_Y,

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111 MISCREG_QUEUE_NRES_ERROR_HEAD,
112 MISCREG_QUEUE_NRES_ERROR_TAIL,
113
114 /* All the data for the TLB packed up in one register. */
115 MISCREG_TLB_DATA,
116 MISCREG_NUMMISCREGS
117};
118
118struct HPSTATE
119{
120 const static uint64_t id = 0x800; // this impl. dependent (id) field m
121 const static uint64_t ibe = 0x400;
122 const static uint64_t red = 0x20;
123 const static uint64_t hpriv = 0x4;
124 const static uint64_t tlz = 0x1;
125};
119BitUnion64(HPSTATE)
120 Bitfield<0> tlz;
121 Bitfield<2> hpriv;
122 Bitfield<5> red;
123 Bitfield<10> ibe;
124 Bitfield<11> id; // this impl. dependent (id) field m
125EndBitUnion(HPSTATE)
126
126
127BitUnion16(PSTATE)
128 Bitfield<1> ie;
129 Bitfield<2> priv;
130 Bitfield<3> am;
131 Bitfield<4> pef;
132 Bitfield<6, 7> mm;
133 Bitfield<8> tle;
134 Bitfield<9> cle;
135 Bitfield<10> pid0;
136 Bitfield<11> pid1;
137EndBitUnion(PSTATE)
127
138
128struct PSTATE
129{
130 const static int cle = 0x200;
131 const static int tle = 0x100;
132 const static int mm = 0xC0;
133 const static int pef = 0x10;
134 const static int am = 0x8;
135 const static int priv = 0x4;
136 const static int ie = 0x2;
137};
138
139struct STS
140{
141 const static int st_idle = 0x00;
142 const static int st_wait = 0x01;
143 const static int st_halt = 0x02;
144 const static int st_run = 0x05;
145 const static int st_spec_run = 0x07;
146 const static int st_spec_rdy = 0x13;

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140{
141 const static int st_idle = 0x00;
142 const static int st_wait = 0x01;
143 const static int st_halt = 0x02;
144 const static int st_run = 0x05;
145 const static int st_spec_run = 0x07;
146 const static int st_spec_rdy = 0x13;

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