1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#ifndef __ARCH_SPARC_MISCREGS_HH__ 33#define __ARCH_SPARC_MISCREGS_HH__ 34 35#include "base/types.hh" 36 37namespace SparcISA 38{
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39 enum MiscRegIndex
40 {
41 /** Ancillary State Registers */
42// MISCREG_Y,
43// MISCREG_CCR,
44 MISCREG_ASI,
45 MISCREG_TICK,
46 MISCREG_FPRS,
47 MISCREG_PCR,
48 MISCREG_PIC,
49 MISCREG_GSR,
50 MISCREG_SOFTINT_SET,
51 MISCREG_SOFTINT_CLR,
52 MISCREG_SOFTINT, /* 10 */
53 MISCREG_TICK_CMPR,
54 MISCREG_STICK,
55 MISCREG_STICK_CMPR,
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39enum MiscRegIndex 40{ 41 /** Ancillary State Registers */ 42// MISCREG_Y, 43// MISCREG_CCR, 44 MISCREG_ASI, 45 MISCREG_TICK, 46 MISCREG_FPRS, 47 MISCREG_PCR, 48 MISCREG_PIC, 49 MISCREG_GSR, 50 MISCREG_SOFTINT_SET, 51 MISCREG_SOFTINT_CLR, 52 MISCREG_SOFTINT, /* 10 */ 53 MISCREG_TICK_CMPR, 54 MISCREG_STICK, 55 MISCREG_STICK_CMPR, |
56
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57 /** Privilged Registers */
58 MISCREG_TPC,
59 MISCREG_TNPC,
60 MISCREG_TSTATE,
61 MISCREG_TT,
62 MISCREG_PRIVTICK,
63 MISCREG_TBA,
64 MISCREG_PSTATE, /* 20 */
65 MISCREG_TL,
66 MISCREG_PIL,
67 MISCREG_CWP,
68// MISCREG_CANSAVE,
69// MISCREG_CANRESTORE,
70// MISCREG_CLEANWIN,
71// MISCREG_OTHERWIN,
72// MISCREG_WSTATE,
73 MISCREG_GL,
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57 /** Privilged Registers */ 58 MISCREG_TPC, 59 MISCREG_TNPC, 60 MISCREG_TSTATE, 61 MISCREG_TT, 62 MISCREG_PRIVTICK, 63 MISCREG_TBA, 64 MISCREG_PSTATE, /* 20 */ 65 MISCREG_TL, 66 MISCREG_PIL, 67 MISCREG_CWP, 68// MISCREG_CANSAVE, 69// MISCREG_CANRESTORE, 70// MISCREG_CLEANWIN, 71// MISCREG_OTHERWIN, 72// MISCREG_WSTATE, 73 MISCREG_GL, |
74
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75 /** Hyper privileged registers */
76 MISCREG_HPSTATE, /* 30 */
77 MISCREG_HTSTATE,
78 MISCREG_HINTP,
79 MISCREG_HTBA,
80 MISCREG_HVER,
81 MISCREG_STRAND_STS_REG,
82 MISCREG_HSTICK_CMPR,
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75 /** Hyper privileged registers */ 76 MISCREG_HPSTATE, /* 30 */ 77 MISCREG_HTSTATE, 78 MISCREG_HINTP, 79 MISCREG_HTBA, 80 MISCREG_HVER, 81 MISCREG_STRAND_STS_REG, 82 MISCREG_HSTICK_CMPR, |
83
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84 /** Floating Point Status Register */
85 MISCREG_FSR,
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84 /** Floating Point Status Register */ 85 MISCREG_FSR, |
86
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87 /** MMU Internal Registers */
88 MISCREG_MMU_P_CONTEXT,
89 MISCREG_MMU_S_CONTEXT, /* 40 */
90 MISCREG_MMU_PART_ID,
91 MISCREG_MMU_LSU_CTRL,
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87 /** MMU Internal Registers */ 88 MISCREG_MMU_P_CONTEXT, 89 MISCREG_MMU_S_CONTEXT, /* 40 */ 90 MISCREG_MMU_PART_ID, 91 MISCREG_MMU_LSU_CTRL, |
92
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93 /** Scratchpad regiscers **/
94 MISCREG_SCRATCHPAD_R0, /* 60 */
95 MISCREG_SCRATCHPAD_R1,
96 MISCREG_SCRATCHPAD_R2,
97 MISCREG_SCRATCHPAD_R3,
98 MISCREG_SCRATCHPAD_R4,
99 MISCREG_SCRATCHPAD_R5,
100 MISCREG_SCRATCHPAD_R6,
101 MISCREG_SCRATCHPAD_R7,
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93 /** Scratchpad regiscers **/ 94 MISCREG_SCRATCHPAD_R0, /* 60 */ 95 MISCREG_SCRATCHPAD_R1, 96 MISCREG_SCRATCHPAD_R2, 97 MISCREG_SCRATCHPAD_R3, 98 MISCREG_SCRATCHPAD_R4, 99 MISCREG_SCRATCHPAD_R5, 100 MISCREG_SCRATCHPAD_R6, 101 MISCREG_SCRATCHPAD_R7, |
102
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103 /* CPU Queue Registers */
104 MISCREG_QUEUE_CPU_MONDO_HEAD,
105 MISCREG_QUEUE_CPU_MONDO_TAIL,
106 MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
107 MISCREG_QUEUE_DEV_MONDO_TAIL,
108 MISCREG_QUEUE_RES_ERROR_HEAD,
109 MISCREG_QUEUE_RES_ERROR_TAIL,
110 MISCREG_QUEUE_NRES_ERROR_HEAD,
111 MISCREG_QUEUE_NRES_ERROR_TAIL,
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103 /* CPU Queue Registers */ 104 MISCREG_QUEUE_CPU_MONDO_HEAD, 105 MISCREG_QUEUE_CPU_MONDO_TAIL, 106 MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */ 107 MISCREG_QUEUE_DEV_MONDO_TAIL, 108 MISCREG_QUEUE_RES_ERROR_HEAD, 109 MISCREG_QUEUE_RES_ERROR_TAIL, 110 MISCREG_QUEUE_NRES_ERROR_HEAD, 111 MISCREG_QUEUE_NRES_ERROR_TAIL, |
112
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113 /* All the data for the TLB packed up in one register. */
114 MISCREG_TLB_DATA,
115 MISCREG_NUMMISCREGS
116 };
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113 /* All the data for the TLB packed up in one register. */ 114 MISCREG_TLB_DATA, 115 MISCREG_NUMMISCREGS 116}; |
117
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118 struct HPSTATE {
119 const static uint64_t id = 0x800; // this impl. dependent (id) field m
120 const static uint64_t ibe = 0x400;
121 const static uint64_t red = 0x20;
122 const static uint64_t hpriv = 0x4;
123 const static uint64_t tlz = 0x1;
124 };
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118struct HPSTATE 119{ 120 const static uint64_t id = 0x800; // this impl. dependent (id) field m 121 const static uint64_t ibe = 0x400; 122 const static uint64_t red = 0x20; 123 const static uint64_t hpriv = 0x4; 124 const static uint64_t tlz = 0x1; 125}; |
126 127
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127 struct PSTATE {
128 const static int cle = 0x200;
129 const static int tle = 0x100;
130 const static int mm = 0xC0;
131 const static int pef = 0x10;
132 const static int am = 0x8;
133 const static int priv = 0x4;
134 const static int ie = 0x2;
135 };
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128struct PSTATE 129{ 130 const static int cle = 0x200; 131 const static int tle = 0x100; 132 const static int mm = 0xC0; 133 const static int pef = 0x10; 134 const static int am = 0x8; 135 const static int priv = 0x4; 136 const static int ie = 0x2; 137}; |
138
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137 struct STS {
138 const static int st_idle = 0x00;
139 const static int st_wait = 0x01;
140 const static int st_halt = 0x02;
141 const static int st_run = 0x05;
142 const static int st_spec_run = 0x07;
143 const static int st_spec_rdy = 0x13;
144 const static int st_ready = 0x19;
145 const static int active = 0x01;
146 const static int speculative = 0x04;
147 const static int shft_id = 8;
148 const static int shft_fsm0 = 31;
149 const static int shft_fsm1 = 26;
150 const static int shft_fsm2 = 21;
151 const static int shft_fsm3 = 16;
152 };
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139struct STS 140{ 141 const static int st_idle = 0x00; 142 const static int st_wait = 0x01; 143 const static int st_halt = 0x02; 144 const static int st_run = 0x05; 145 const static int st_spec_run = 0x07; 146 const static int st_spec_rdy = 0x13; 147 const static int st_ready = 0x19; 148 const static int active = 0x01; 149 const static int speculative = 0x04; 150 const static int shft_id = 8; 151 const static int shft_fsm0 = 31; 152 const static int shft_fsm1 = 26; 153 const static int shft_fsm2 = 21; 154 const static int shft_fsm3 = 16; 155}; |
156 157
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155 const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
156 const int NumMiscRegs = MISCREG_NUMMISCREGS;
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158const int NumMiscArchRegs = MISCREG_NUMMISCREGS; 159const int NumMiscRegs = MISCREG_NUMMISCREGS; 160 |
161} 162 163#endif
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