39,55c39,55
< enum MiscRegIndex
< {
< /** Ancillary State Registers */
< // MISCREG_Y,
< // MISCREG_CCR,
< MISCREG_ASI,
< MISCREG_TICK,
< MISCREG_FPRS,
< MISCREG_PCR,
< MISCREG_PIC,
< MISCREG_GSR,
< MISCREG_SOFTINT_SET,
< MISCREG_SOFTINT_CLR,
< MISCREG_SOFTINT, /* 10 */
< MISCREG_TICK_CMPR,
< MISCREG_STICK,
< MISCREG_STICK_CMPR,
---
> enum MiscRegIndex
> {
> /** Ancillary State Registers */
> // MISCREG_Y,
> // MISCREG_CCR,
> MISCREG_ASI,
> MISCREG_TICK,
> MISCREG_FPRS,
> MISCREG_PCR,
> MISCREG_PIC,
> MISCREG_GSR,
> MISCREG_SOFTINT_SET,
> MISCREG_SOFTINT_CLR,
> MISCREG_SOFTINT, /* 10 */
> MISCREG_TICK_CMPR,
> MISCREG_STICK,
> MISCREG_STICK_CMPR,
57,73c57,73
< /** Privilged Registers */
< MISCREG_TPC,
< MISCREG_TNPC,
< MISCREG_TSTATE,
< MISCREG_TT,
< MISCREG_PRIVTICK,
< MISCREG_TBA,
< MISCREG_PSTATE, /* 20 */
< MISCREG_TL,
< MISCREG_PIL,
< MISCREG_CWP,
< // MISCREG_CANSAVE,
< // MISCREG_CANRESTORE,
< // MISCREG_CLEANWIN,
< // MISCREG_OTHERWIN,
< // MISCREG_WSTATE,
< MISCREG_GL,
---
> /** Privilged Registers */
> MISCREG_TPC,
> MISCREG_TNPC,
> MISCREG_TSTATE,
> MISCREG_TT,
> MISCREG_PRIVTICK,
> MISCREG_TBA,
> MISCREG_PSTATE, /* 20 */
> MISCREG_TL,
> MISCREG_PIL,
> MISCREG_CWP,
> // MISCREG_CANSAVE,
> // MISCREG_CANRESTORE,
> // MISCREG_CLEANWIN,
> // MISCREG_OTHERWIN,
> // MISCREG_WSTATE,
> MISCREG_GL,
75,82c75,82
< /** Hyper privileged registers */
< MISCREG_HPSTATE, /* 30 */
< MISCREG_HTSTATE,
< MISCREG_HINTP,
< MISCREG_HTBA,
< MISCREG_HVER,
< MISCREG_STRAND_STS_REG,
< MISCREG_HSTICK_CMPR,
---
> /** Hyper privileged registers */
> MISCREG_HPSTATE, /* 30 */
> MISCREG_HTSTATE,
> MISCREG_HINTP,
> MISCREG_HTBA,
> MISCREG_HVER,
> MISCREG_STRAND_STS_REG,
> MISCREG_HSTICK_CMPR,
84,85c84,85
< /** Floating Point Status Register */
< MISCREG_FSR,
---
> /** Floating Point Status Register */
> MISCREG_FSR,
87,91c87,91
< /** MMU Internal Registers */
< MISCREG_MMU_P_CONTEXT,
< MISCREG_MMU_S_CONTEXT, /* 40 */
< MISCREG_MMU_PART_ID,
< MISCREG_MMU_LSU_CTRL,
---
> /** MMU Internal Registers */
> MISCREG_MMU_P_CONTEXT,
> MISCREG_MMU_S_CONTEXT, /* 40 */
> MISCREG_MMU_PART_ID,
> MISCREG_MMU_LSU_CTRL,
93,101c93,101
< /** Scratchpad regiscers **/
< MISCREG_SCRATCHPAD_R0, /* 60 */
< MISCREG_SCRATCHPAD_R1,
< MISCREG_SCRATCHPAD_R2,
< MISCREG_SCRATCHPAD_R3,
< MISCREG_SCRATCHPAD_R4,
< MISCREG_SCRATCHPAD_R5,
< MISCREG_SCRATCHPAD_R6,
< MISCREG_SCRATCHPAD_R7,
---
> /** Scratchpad regiscers **/
> MISCREG_SCRATCHPAD_R0, /* 60 */
> MISCREG_SCRATCHPAD_R1,
> MISCREG_SCRATCHPAD_R2,
> MISCREG_SCRATCHPAD_R3,
> MISCREG_SCRATCHPAD_R4,
> MISCREG_SCRATCHPAD_R5,
> MISCREG_SCRATCHPAD_R6,
> MISCREG_SCRATCHPAD_R7,
103,111c103,111
< /* CPU Queue Registers */
< MISCREG_QUEUE_CPU_MONDO_HEAD,
< MISCREG_QUEUE_CPU_MONDO_TAIL,
< MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
< MISCREG_QUEUE_DEV_MONDO_TAIL,
< MISCREG_QUEUE_RES_ERROR_HEAD,
< MISCREG_QUEUE_RES_ERROR_TAIL,
< MISCREG_QUEUE_NRES_ERROR_HEAD,
< MISCREG_QUEUE_NRES_ERROR_TAIL,
---
> /* CPU Queue Registers */
> MISCREG_QUEUE_CPU_MONDO_HEAD,
> MISCREG_QUEUE_CPU_MONDO_TAIL,
> MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
> MISCREG_QUEUE_DEV_MONDO_TAIL,
> MISCREG_QUEUE_RES_ERROR_HEAD,
> MISCREG_QUEUE_RES_ERROR_TAIL,
> MISCREG_QUEUE_NRES_ERROR_HEAD,
> MISCREG_QUEUE_NRES_ERROR_TAIL,
113,116c113,116
< /* All the data for the TLB packed up in one register. */
< MISCREG_TLB_DATA,
< MISCREG_NUMMISCREGS
< };
---
> /* All the data for the TLB packed up in one register. */
> MISCREG_TLB_DATA,
> MISCREG_NUMMISCREGS
> };
118,124c118,125
< struct HPSTATE {
< const static uint64_t id = 0x800; // this impl. dependent (id) field m
< const static uint64_t ibe = 0x400;
< const static uint64_t red = 0x20;
< const static uint64_t hpriv = 0x4;
< const static uint64_t tlz = 0x1;
< };
---
> struct HPSTATE
> {
> const static uint64_t id = 0x800; // this impl. dependent (id) field m
> const static uint64_t ibe = 0x400;
> const static uint64_t red = 0x20;
> const static uint64_t hpriv = 0x4;
> const static uint64_t tlz = 0x1;
> };
127,135c128,137
< struct PSTATE {
< const static int cle = 0x200;
< const static int tle = 0x100;
< const static int mm = 0xC0;
< const static int pef = 0x10;
< const static int am = 0x8;
< const static int priv = 0x4;
< const static int ie = 0x2;
< };
---
> struct PSTATE
> {
> const static int cle = 0x200;
> const static int tle = 0x100;
> const static int mm = 0xC0;
> const static int pef = 0x10;
> const static int am = 0x8;
> const static int priv = 0x4;
> const static int ie = 0x2;
> };
137,152c139,155
< struct STS {
< const static int st_idle = 0x00;
< const static int st_wait = 0x01;
< const static int st_halt = 0x02;
< const static int st_run = 0x05;
< const static int st_spec_run = 0x07;
< const static int st_spec_rdy = 0x13;
< const static int st_ready = 0x19;
< const static int active = 0x01;
< const static int speculative = 0x04;
< const static int shft_id = 8;
< const static int shft_fsm0 = 31;
< const static int shft_fsm1 = 26;
< const static int shft_fsm2 = 21;
< const static int shft_fsm3 = 16;
< };
---
> struct STS
> {
> const static int st_idle = 0x00;
> const static int st_wait = 0x01;
> const static int st_halt = 0x02;
> const static int st_run = 0x05;
> const static int st_spec_run = 0x07;
> const static int st_spec_rdy = 0x13;
> const static int st_ready = 0x19;
> const static int active = 0x01;
> const static int speculative = 0x04;
> const static int shft_id = 8;
> const static int shft_fsm0 = 31;
> const static int shft_fsm1 = 26;
> const static int shft_fsm2 = 21;
> const static int shft_fsm3 = 16;
> };
155,156c158,160
< const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
< const int NumMiscRegs = MISCREG_NUMMISCREGS;
---
> const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
> const int NumMiscRegs = MISCREG_NUMMISCREGS;
>