isa_traits.hh (8542:7230ff0738e3) isa_traits.hh (8739:925f15f96322)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 */
31
32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
33#define __ARCH_SPARC_ISA_TRAITS_HH__
34
35#include "arch/sparc/sparc_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/types.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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30 */
31
32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
33#define __ARCH_SPARC_ISA_TRAITS_HH__
34
35#include "arch/sparc/sparc_traits.hh"
36#include "arch/sparc/types.hh"
37#include "base/types.hh"
38#include "config/full_system.hh"
39#include "cpu/static_inst_fwd.hh"
40
41namespace BigEndianGuest {}
42
43namespace SparcISA
44{
45const int MachineBytes = 8;
46

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73
74/////////// TLB Stuff ////////////
75const Addr StartVAddrHole = ULL(0x0000800000000000);
76const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
77const Addr VAddrAMask = ULL(0xFFFFFFFF);
78const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
79const Addr BytesInPageMask = ULL(0x1FFF);
80
38#include "cpu/static_inst_fwd.hh"
39
40namespace BigEndianGuest {}
41
42namespace SparcISA
43{
44const int MachineBytes = 8;
45

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72
73/////////// TLB Stuff ////////////
74const Addr StartVAddrHole = ULL(0x0000800000000000);
75const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
76const Addr VAddrAMask = ULL(0xFFFFFFFF);
77const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
78const Addr BytesInPageMask = ULL(0x1FFF);
79
81#if FULL_SYSTEM
82enum InterruptTypes
83{
84 IT_TRAP_LEVEL_ZERO,
85 IT_HINTP,
86 IT_INT_VEC,
87 IT_CPU_MONDO,
88 IT_DEV_MONDO,
89 IT_RES_ERROR,
90 IT_SOFT_INT,
91 NumInterruptTypes
92};
93
80enum InterruptTypes
81{
82 IT_TRAP_LEVEL_ZERO,
83 IT_HINTP,
84 IT_INT_VEC,
85 IT_CPU_MONDO,
86 IT_DEV_MONDO,
87 IT_RES_ERROR,
88 IT_SOFT_INT,
89 NumInterruptTypes
90};
91
94#endif
95
96// Memory accesses cannot be unaligned
97const bool HasUnalignedMemAcc = false;
98}
99
100#endif // __ARCH_SPARC_ISA_TRAITS_HH__
92// Memory accesses cannot be unaligned
93const bool HasUnalignedMemAcc = false;
94}
95
96#endif // __ARCH_SPARC_ISA_TRAITS_HH__