isa_traits.hh (7580:6f77f379a594) | isa_traits.hh (7741:340b6f01d69b) |
---|---|
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "config/full_system.hh" 39 40class StaticInstPtr; 41 42namespace BigEndianGuest {} 43 44namespace SparcISA 45{ | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "config/full_system.hh" 39 40class StaticInstPtr; 41 42namespace BigEndianGuest {} 43 44namespace SparcISA 45{ |
46 const int MachineBytes = 8; | 46const int MachineBytes = 8; |
47 | 47 |
48 //This makes sure the big endian versions of certain functions are used. 49 using namespace BigEndianGuest; | 48// This makes sure the big endian versions of certain functions are used. 49using namespace BigEndianGuest; |
50 | 50 |
51 // SPARC has a delay slot 52 #define ISA_HAS_DELAY_SLOT 1 | 51// SPARC has a delay slot 52#define ISA_HAS_DELAY_SLOT 1 |
53 | 53 |
54 // SPARC NOP (sethi %(hi(0), g0) 55 const MachInst NoopMachInst = 0x01000000; | 54// SPARC NOP (sethi %(hi(0), g0) 55const MachInst NoopMachInst = 0x01000000; |
56 | 56 |
57 //8K. This value is implmentation specific; and should probably 58 //be somewhere else. 59 const int LogVMPageSize = 13; 60 const int VMPageSize = (1 << LogVMPageSize); | 57// 8K. This value is implmentation specific; and should probably 58// be somewhere else. 59const int LogVMPageSize = 13; 60const int VMPageSize = (1 << LogVMPageSize); |
61 | 61 |
62 // real address virtual mapping 63 // sort of like alpha super page, but less frequently used 64 const Addr SegKPMEnd = ULL(0xfffffffc00000000); 65 const Addr SegKPMBase = ULL(0xfffffac000000000); | 62// real address virtual mapping 63// sort of like alpha super page, but less frequently used 64const Addr SegKPMEnd = ULL(0xfffffffc00000000); 65const Addr SegKPMBase = ULL(0xfffffac000000000); |
66 | 66 |
67 //Why does both the previous set of constants and this one exist? 68 const int PageShift = 13; 69 const int PageBytes = 1ULL << PageShift; | 67// Why does both the previous set of constants and this one exist? 68const int PageShift = 13; 69const int PageBytes = 1ULL << PageShift; |
70 | 70 |
71 const int BranchPredAddrShiftAmt = 2; | 71const int BranchPredAddrShiftAmt = 2; |
72 | 72 |
73 StaticInstPtr decodeInst(ExtMachInst); | 73StaticInstPtr decodeInst(ExtMachInst); |
74 | 74 |
75 /////////// TLB Stuff //////////// 76 const Addr StartVAddrHole = ULL(0x0000800000000000); 77 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 78 const Addr VAddrAMask = ULL(0xFFFFFFFF); 79 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 80 const Addr BytesInPageMask = ULL(0x1FFF); | 75/////////// TLB Stuff //////////// 76const Addr StartVAddrHole = ULL(0x0000800000000000); 77const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 78const Addr VAddrAMask = ULL(0xFFFFFFFF); 79const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 80const Addr BytesInPageMask = ULL(0x1FFF); |
81 82#if FULL_SYSTEM | 81 82#if FULL_SYSTEM |
83 enum InterruptTypes 84 { 85 IT_TRAP_LEVEL_ZERO, 86 IT_HINTP, 87 IT_INT_VEC, 88 IT_CPU_MONDO, 89 IT_DEV_MONDO, 90 IT_RES_ERROR, 91 IT_SOFT_INT, 92 NumInterruptTypes 93 }; | 83enum InterruptTypes 84{ 85 IT_TRAP_LEVEL_ZERO, 86 IT_HINTP, 87 IT_INT_VEC, 88 IT_CPU_MONDO, 89 IT_DEV_MONDO, 90 IT_RES_ERROR, 91 IT_SOFT_INT, 92 NumInterruptTypes 93}; |
94 95#endif 96 97// Memory accesses cannot be unaligned 98const bool HasUnalignedMemAcc = false; 99} 100 101#endif // __ARCH_SPARC_ISA_TRAITS_HH__ | 94 95#endif 96 97// Memory accesses cannot be unaligned 98const bool HasUnalignedMemAcc = false; 99} 100 101#endif // __ARCH_SPARC_ISA_TRAITS_HH__ |