isa_traits.hh (6326:008930a4ace5) isa_traits.hh (6329:5d8b91875859)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
33#define __ARCH_SPARC_ISA_TRAITS_HH__
34
35#include "arch/sparc/types.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
33#define __ARCH_SPARC_ISA_TRAITS_HH__
34
35#include "arch/sparc/types.hh"
36#include "arch/sparc/max_inst_regs.hh"
37#include "arch/sparc/sparc_traits.hh"
38#include "base/types.hh"
39#include "config/full_system.hh"
40
41class StaticInstPtr;
42
43namespace BigEndianGuest {}
44
45namespace SparcISA
46{
47 const int MachineBytes = 8;
48
49 //This makes sure the big endian versions of certain functions are used.
50 using namespace BigEndianGuest;
36#include "arch/sparc/sparc_traits.hh"
37#include "base/types.hh"
38#include "config/full_system.hh"
39
40class StaticInstPtr;
41
42namespace BigEndianGuest {}
43
44namespace SparcISA
45{
46 const int MachineBytes = 8;
47
48 //This makes sure the big endian versions of certain functions are used.
49 using namespace BigEndianGuest;
51 using SparcISAInst::MaxInstSrcRegs;
52 using SparcISAInst::MaxInstDestRegs;
53
54 // SPARC has a delay slot
55 #define ISA_HAS_DELAY_SLOT 1
56
57 // SPARC NOP (sethi %(hi(0), g0)
58 const MachInst NoopMachInst = 0x01000000;
59
50
51 // SPARC has a delay slot
52 #define ISA_HAS_DELAY_SLOT 1
53
54 // SPARC NOP (sethi %(hi(0), g0)
55 const MachInst NoopMachInst = 0x01000000;
56
60 // These enumerate all the registers for dependence tracking.
61 enum DependenceTags {
62 FP_Base_DepTag = 32*3+9,
63 Ctrl_Base_DepTag = FP_Base_DepTag + 64
64 };
65
66 // semantically meaningful register indices
67 const int ZeroReg = 0; // architecturally meaningful
68 // the rest of these depend on the ABI
69 const int ReturnAddressReg = 31; // post call, precall is 15
70 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
71 const int StackPointerReg = 14;
72 const int FramePointerReg = 30;
73
74 // Some OS syscall use a second register (o1) to return a second value
75 const int SyscallPseudoReturnReg = 9;
76
77 //8K. This value is implmentation specific; and should probably
78 //be somewhere else.
79 const int LogVMPageSize = 13;
80 const int VMPageSize = (1 << LogVMPageSize);
81
82 // real address virtual mapping
83 // sort of like alpha super page, but less frequently used
84 const Addr SegKPMEnd = ULL(0xfffffffc00000000);

--- 39 unchanged lines hidden --- 		57 //8K. This value is implmentation specific; and should probably
58 //be somewhere else.
59 const int LogVMPageSize = 13;
60 const int VMPageSize = (1 << LogVMPageSize);
61
62 // real address virtual mapping
63 // sort of like alpha super page, but less frequently used
64 const Addr SegKPMEnd = ULL(0xfffffffc00000000);

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