isa_traits.hh (3893:e2a358430839) | isa_traits.hh (3918:1f9a98d198e8) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 45 unchanged lines hidden (view full) --- 54 #define ISA_HAS_DELAY_SLOT 1 55 56 // SPARC NOP (sethi %(hi(0), g0) 57 const MachInst NoopMachInst = 0x01000000; 58 59 // These enumerate all the registers for dependence tracking. 60 enum DependenceTags { 61 FP_Base_DepTag = 33, | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 45 unchanged lines hidden (view full) --- 54 #define ISA_HAS_DELAY_SLOT 1 55 56 // SPARC NOP (sethi %(hi(0), g0) 57 const MachInst NoopMachInst = 0x01000000; 58 59 // These enumerate all the registers for dependence tracking. 60 enum DependenceTags { 61 FP_Base_DepTag = 33, |
62 Ctrl_Base_DepTag = 97, | 62 Ctrl_Base_DepTag = 97 |
63 }; 64 65 // semantically meaningful register indices 66 const int ZeroReg = 0; // architecturally meaningful 67 // the rest of these depend on the ABI 68 const int StackPointerReg = 14; 69 const int ReturnAddressReg = 31; // post call, precall is 15 70 const int ReturnValueReg = 8; // Post return, 24 is pre-return. --- 20 unchanged lines hidden (view full) --- 91 const int PageShift = 13; 92 const int PageBytes = 1ULL << PageShift; 93 94 const int BranchPredAddrShiftAmt = 2; 95 96 StaticInstPtr decodeInst(ExtMachInst); 97 98#if FULL_SYSTEM | 63 }; 64 65 // semantically meaningful register indices 66 const int ZeroReg = 0; // architecturally meaningful 67 // the rest of these depend on the ABI 68 const int StackPointerReg = 14; 69 const int ReturnAddressReg = 31; // post call, precall is 15 70 const int ReturnValueReg = 8; // Post return, 24 is pre-return. --- 20 unchanged lines hidden (view full) --- 91 const int PageShift = 13; 92 const int PageBytes = 1ULL << PageShift; 93 94 const int BranchPredAddrShiftAmt = 2; 95 96 StaticInstPtr decodeInst(ExtMachInst); 97 98#if FULL_SYSTEM |
99 ////////// Interrupt Stuff /////////// 100 enum InterruptLevels 101 { 102 INTLEVEL_MIN = 1, 103 INTLEVEL_MAX = 15, 104 105 NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN 106 }; 107 |
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99 // I don't know what it's for, so I don't 100 // know what SPARC's value should be 101 // For loading... XXX This maybe could be USegEnd?? --ali 102 const Addr LoadAddrMask = ULL(0xffffffffff); 103 104 /////////// TLB Stuff //////////// 105 const Addr StartVAddrHole = ULL(0x0000800000000000); 106 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 107 const Addr VAddrAMask = ULL(0xFFFFFFFF); 108 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 109 const Addr BytesInPageMask = ULL(0x1FFF); 110 111#endif 112} 113 114#endif // __ARCH_SPARC_ISA_TRAITS_HH__ | 108 // I don't know what it's for, so I don't 109 // know what SPARC's value should be 110 // For loading... XXX This maybe could be USegEnd?? --ali 111 const Addr LoadAddrMask = ULL(0xffffffffff); 112 113 /////////// TLB Stuff //////////// 114 const Addr StartVAddrHole = ULL(0x0000800000000000); 115 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 116 const Addr VAddrAMask = ULL(0xFFFFFFFF); 117 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 118 const Addr BytesInPageMask = ULL(0x1FFF); 119 120#endif 121} 122 123#endif // __ARCH_SPARC_ISA_TRAITS_HH__ |