isa_traits.hh (3761:b7c7f547d5a3) isa_traits.hh (3804:fa7a01dddc7a)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
32#define __ARCH_SPARC_ISA_TRAITS_HH__
33
34#include "arch/sparc/types.hh"
30 */
31
32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
33#define __ARCH_SPARC_ISA_TRAITS_HH__
34
35#include "arch/sparc/types.hh"
35#include "arch/sparc/sparc_traits.hh"
36#include "base/misc.hh"
36#include "config/full_system.hh"
37#include "config/full_system.hh"
38#include "sim/host.hh"
37
39
40class ThreadContext;
41class FastCPU;
42//class FullCPU;
43class Checkpoint;
44
45class StaticInst;
38class StaticInstPtr;
39
40namespace BigEndianGuest {}
41
46class StaticInstPtr;
47
48namespace BigEndianGuest {}
49
42#if FULL_SYSTEM
43#include "arch/sparc/isa_fullsys_traits.hh"
44#endif
45
46namespace SparcISA
47{
48 class RegFile;
49
50 //This makes sure the big endian versions of certain functions are used.
51 using namespace BigEndianGuest;
52
53 // SPARC has a delay slot
54 #define ISA_HAS_DELAY_SLOT 1
55
56 // SPARC NOP (sethi %(hi(0), g0)
57 const MachInst NoopMachInst = 0x01000000;
58
50namespace SparcISA
51{
52 class RegFile;
53
54 //This makes sure the big endian versions of certain functions are used.
55 using namespace BigEndianGuest;
56
57 // SPARC has a delay slot
58 #define ISA_HAS_DELAY_SLOT 1
59
60 // SPARC NOP (sethi %(hi(0), g0)
61 const MachInst NoopMachInst = 0x01000000;
62
63 const int NumRegularIntRegs = 32;
64 const int NumMicroIntRegs = 1;
65 const int NumIntRegs =
66 NumRegularIntRegs +
67 NumMicroIntRegs;
68 const int NumFloatRegs = 64;
69 const int NumMiscRegs = 40;
70
59 // These enumerate all the registers for dependence tracking.
60 enum DependenceTags {
71 // These enumerate all the registers for dependence tracking.
72 enum DependenceTags {
61 FP_Base_DepTag = 32*3+8,
62 Ctrl_Base_DepTag = FP_Base_DepTag + 64,
73 // 0..31 are the integer regs 0..31
74 // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
75 FP_Base_DepTag = NumIntRegs,
76 Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs,
63 };
64
77 };
78
79
80 // MAXTL - maximum trap level
81 const int MaxPTL = 2;
82 const int MaxTL = 6;
83 const int MaxGL = 3;
84 const int MaxPGL = 2;
85
86 // NWINDOWS - number of register windows, can be 3 to 32
87 const int NWindows = 8;
88
65 // semantically meaningful register indices
66 const int ZeroReg = 0; // architecturally meaningful
67 // the rest of these depend on the ABI
68 const int StackPointerReg = 14;
69 const int ReturnAddressReg = 31; // post call, precall is 15
70 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
71 const int FramePointerReg = 30;
72 const int ArgumentReg0 = 8;

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84
85 //8K. This value is implmentation specific; and should probably
86 //be somewhere else.
87 const int LogVMPageSize = 13;
88 const int VMPageSize = (1 << LogVMPageSize);
89
90 //Why does both the previous set of constants and this one exist?
91 const int PageShift = 13;
89 // semantically meaningful register indices
90 const int ZeroReg = 0; // architecturally meaningful
91 // the rest of these depend on the ABI
92 const int StackPointerReg = 14;
93 const int ReturnAddressReg = 31; // post call, precall is 15
94 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
95 const int FramePointerReg = 30;
96 const int ArgumentReg0 = 8;

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108
109 //8K. This value is implmentation specific; and should probably
110 //be somewhere else.
111 const int LogVMPageSize = 13;
112 const int VMPageSize = (1 << LogVMPageSize);
113
114 //Why does both the previous set of constants and this one exist?
115 const int PageShift = 13;
92 const int PageBytes = 1ULL << PageShift;
116 const int PageBytes = ULL(1) << PageShift;
93
94 const int BranchPredAddrShiftAmt = 2;
95
117
118 const int BranchPredAddrShiftAmt = 2;
119
120 const int MachineBytes = 8;
121 const int WordBytes = 4;
122 const int HalfwordBytes = 2;
123 const int ByteBytes = 1;
124
125 void serialize(std::ostream & os);
126
127 void unserialize(Checkpoint *cp, const std::string &section);
128
96 StaticInstPtr decodeInst(ExtMachInst);
129 StaticInstPtr decodeInst(ExtMachInst);
130
131 // return a no-op instruction... used for instruction fetch faults
132 extern const MachInst NoopMachInst;
133
134#if FULL_SYSTEM
135 ////////// Interrupt Stuff ///////////
136 enum InterruptLevels
137 {
138 INTLEVEL_MIN = 1,
139 INTLEVEL_MAX = 15,
140
141 NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN
142 };
143
144 // I don't know what it's for, so I don't
145 // know what SPARC's value should be
146 // For loading... XXX This maybe could be USegEnd?? --ali
147 const Addr LoadAddrMask = ULL(0xffffffffff);
148
149 /////////// TLB Stuff ////////////
150 const Addr StartVAddrHole = ULL(0x0000800000000000);
151 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
152 const Addr VAddrAMask = ULL(0xFFFFFFFF);
153 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
154 const Addr BytesInPageMask = ULL(0x1FFF);
155
156#endif
97}
98
99#endif // __ARCH_SPARC_ISA_TRAITS_HH__
157}
158
159#endif // __ARCH_SPARC_ISA_TRAITS_HH__