1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Ali Saidi 30 */ 31 32#ifndef __ARCH_SPARC_ISA_TRAITS_HH__ 33#define __ARCH_SPARC_ISA_TRAITS_HH__ 34 35#include "arch/sparc/types.hh"
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36#include "base/misc.hh"
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36#include "arch/sparc/sparc_traits.hh" |
37#include "config/full_system.hh"
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38#include "sim/host.hh"
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38
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40class ThreadContext;
41class FastCPU;
42//class FullCPU;
43class Checkpoint;
44
45class StaticInst;
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39class StaticInstPtr; 40 41namespace BigEndianGuest {} 42 43namespace SparcISA 44{ 45 class RegFile; 46 47 //This makes sure the big endian versions of certain functions are used. 48 using namespace BigEndianGuest; 49 50 // SPARC has a delay slot 51 #define ISA_HAS_DELAY_SLOT 1 52 53 // SPARC NOP (sethi %(hi(0), g0) 54 const MachInst NoopMachInst = 0x01000000; 55
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63 const int NumRegularIntRegs = 32;
64 const int NumMicroIntRegs = 1;
65 const int NumIntRegs =
66 NumRegularIntRegs +
67 NumMicroIntRegs;
68 const int NumFloatRegs = 64;
69 const int NumMiscRegs = 40;
70
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56 // These enumerate all the registers for dependence tracking. 57 enum DependenceTags {
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73 // 0..31 are the integer regs 0..31
74 // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
75 FP_Base_DepTag = NumIntRegs,
76 Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs,
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58 FP_Base_DepTag = 33, 59 Ctrl_Base_DepTag = 97, |
60 }; 61
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79
80 // MAXTL - maximum trap level
81 const int MaxPTL = 2;
82 const int MaxTL = 6;
83 const int MaxGL = 3;
84 const int MaxPGL = 2;
85
86 // NWINDOWS - number of register windows, can be 3 to 32
87 const int NWindows = 8;
88
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62 // semantically meaningful register indices 63 const int ZeroReg = 0; // architecturally meaningful 64 // the rest of these depend on the ABI 65 const int StackPointerReg = 14; 66 const int ReturnAddressReg = 31; // post call, precall is 15 67 const int ReturnValueReg = 8; // Post return, 24 is pre-return. 68 const int FramePointerReg = 30; 69 const int ArgumentReg0 = 8; 70 const int ArgumentReg1 = 9; 71 const int ArgumentReg2 = 10; 72 const int ArgumentReg3 = 11; 73 const int ArgumentReg4 = 12; 74 const int ArgumentReg5 = 13; 75 // Some OS syscall use a second register (o1) to return a second value 76 const int SyscallPseudoReturnReg = ArgumentReg1; 77 78 //XXX These numbers are bogus 79 const int MaxInstSrcRegs = 8; 80 const int MaxInstDestRegs = 9; 81 82 //8K. This value is implmentation specific; and should probably 83 //be somewhere else. 84 const int LogVMPageSize = 13; 85 const int VMPageSize = (1 << LogVMPageSize); 86 87 //Why does both the previous set of constants and this one exist? 88 const int PageShift = 13;
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116 const int PageBytes = ULL(1) << PageShift;
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89 const int PageBytes = 1ULL << PageShift; |
90 91 const int BranchPredAddrShiftAmt = 2; 92
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120 const int MachineBytes = 8;
121 const int WordBytes = 4;
122 const int HalfwordBytes = 2;
123 const int ByteBytes = 1;
124
125 void serialize(std::ostream & os);
126
127 void unserialize(Checkpoint *cp, const std::string §ion);
128
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93 StaticInstPtr decodeInst(ExtMachInst); 94
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131 // return a no-op instruction... used for instruction fetch faults
132 extern const MachInst NoopMachInst;
133
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95#if FULL_SYSTEM 96 ////////// Interrupt Stuff /////////// 97 enum InterruptLevels 98 { 99 INTLEVEL_MIN = 1, 100 INTLEVEL_MAX = 15, 101 102 NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN 103 }; 104 105 // I don't know what it's for, so I don't 106 // know what SPARC's value should be 107 // For loading... XXX This maybe could be USegEnd?? --ali 108 const Addr LoadAddrMask = ULL(0xffffffffff); 109 110 /////////// TLB Stuff //////////// 111 const Addr StartVAddrHole = ULL(0x0000800000000000); 112 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF); 113 const Addr VAddrAMask = ULL(0xFFFFFFFF); 114 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF); 115 const Addr BytesInPageMask = ULL(0x1FFF); 116 117#endif 118} 119 120#endif // __ARCH_SPARC_ISA_TRAITS_HH__
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