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< #include "base/misc.hh"
---
> #include "arch/sparc/sparc_traits.hh"
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< #include "sim/host.hh"
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< class ThreadContext;
< class FastCPU;
< //class FullCPU;
< class Checkpoint;
<
< class StaticInst;
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< const int NumRegularIntRegs = 32;
< const int NumMicroIntRegs = 1;
< const int NumIntRegs =
< NumRegularIntRegs +
< NumMicroIntRegs;
< const int NumFloatRegs = 64;
< const int NumMiscRegs = 40;
<
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< // 0..31 are the integer regs 0..31
< // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
< FP_Base_DepTag = NumIntRegs,
< Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs,
---
> FP_Base_DepTag = 33,
> Ctrl_Base_DepTag = 97,
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<
< // MAXTL - maximum trap level
< const int MaxPTL = 2;
< const int MaxTL = 6;
< const int MaxGL = 3;
< const int MaxPGL = 2;
<
< // NWINDOWS - number of register windows, can be 3 to 32
< const int NWindows = 8;
<
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< const int MachineBytes = 8;
< const int WordBytes = 4;
< const int HalfwordBytes = 2;
< const int ByteBytes = 1;
<
< void serialize(std::ostream & os);
<
< void unserialize(Checkpoint *cp, const std::string &section);
<
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<
< // return a no-op instruction... used for instruction fetch faults
< extern const MachInst NoopMachInst;