1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
32#define __ARCH_SPARC_ISA_TRAITS_HH__
33
34#include "arch/sparc/types.hh"
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
32#define __ARCH_SPARC_ISA_TRAITS_HH__
33
34#include "arch/sparc/types.hh"
|
35#include "base/misc.hh"
| 35#include "arch/sparc/sparc_traits.hh"
|
36#include "config/full_system.hh"
| 36#include "config/full_system.hh"
|
37#include "sim/host.hh"
| |
38
| 37
|
39class ThreadContext;
40class FastCPU;
41//class FullCPU;
42class Checkpoint;
43
44class StaticInst;
| |
45class StaticInstPtr;
46
47namespace BigEndianGuest {}
48
49#if FULL_SYSTEM
50#include "arch/sparc/isa_fullsys_traits.hh"
51#endif
52
53namespace SparcISA
54{
55 class RegFile;
56
57 //This makes sure the big endian versions of certain functions are used.
58 using namespace BigEndianGuest;
59
60 // SPARC has a delay slot
61 #define ISA_HAS_DELAY_SLOT 1
62
63 // SPARC NOP (sethi %(hi(0), g0)
64 const MachInst NoopMachInst = 0x01000000;
65
| 38class StaticInstPtr;
39
40namespace BigEndianGuest {}
41
42#if FULL_SYSTEM
43#include "arch/sparc/isa_fullsys_traits.hh"
44#endif
45
46namespace SparcISA
47{
48 class RegFile;
49
50 //This makes sure the big endian versions of certain functions are used.
51 using namespace BigEndianGuest;
52
53 // SPARC has a delay slot
54 #define ISA_HAS_DELAY_SLOT 1
55
56 // SPARC NOP (sethi %(hi(0), g0)
57 const MachInst NoopMachInst = 0x01000000;
58
|
66 const int NumRegularIntRegs = 32;
67 const int NumMicroIntRegs = 1;
68 const int NumIntRegs =
69 NumRegularIntRegs +
70 NumMicroIntRegs;
71 const int NumFloatRegs = 64;
72 const int NumMiscRegs = 40;
73
| |
74 // These enumerate all the registers for dependence tracking.
75 enum DependenceTags {
| 59 // These enumerate all the registers for dependence tracking.
60 enum DependenceTags {
|
76 // 0..31 are the integer regs 0..31
77 // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
78 FP_Base_DepTag = NumIntRegs,
79 Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs,
| 61 FP_Base_DepTag = 33,
62 Ctrl_Base_DepTag = 97,
|
80 };
81
| 63 };
64
|
82
83 // MAXTL - maximum trap level
84 const int MaxPTL = 2;
85 const int MaxTL = 6;
86 const int MaxGL = 3;
87 const int MaxPGL = 2;
88
89 // NWINDOWS - number of register windows, can be 3 to 32
90 const int NWindows = 8;
91
| |
92 // semantically meaningful register indices
93 const int ZeroReg = 0; // architecturally meaningful
94 // the rest of these depend on the ABI
95 const int StackPointerReg = 14;
96 const int ReturnAddressReg = 31; // post call, precall is 15
97 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
98 const int FramePointerReg = 30;
99 const int ArgumentReg0 = 8;
100 const int ArgumentReg1 = 9;
101 const int ArgumentReg2 = 10;
102 const int ArgumentReg3 = 11;
103 const int ArgumentReg4 = 12;
104 const int ArgumentReg5 = 13;
105 // Some OS syscall use a second register (o1) to return a second value
106 const int SyscallPseudoReturnReg = ArgumentReg1;
107
108 //XXX These numbers are bogus
109 const int MaxInstSrcRegs = 8;
110 const int MaxInstDestRegs = 9;
111
112 //8K. This value is implmentation specific; and should probably
113 //be somewhere else.
114 const int LogVMPageSize = 13;
115 const int VMPageSize = (1 << LogVMPageSize);
116
117 //Why does both the previous set of constants and this one exist?
118 const int PageShift = 13;
119 const int PageBytes = ULL(1) << PageShift;
120
121 const int BranchPredAddrShiftAmt = 2;
122
| 65 // semantically meaningful register indices
66 const int ZeroReg = 0; // architecturally meaningful
67 // the rest of these depend on the ABI
68 const int StackPointerReg = 14;
69 const int ReturnAddressReg = 31; // post call, precall is 15
70 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
71 const int FramePointerReg = 30;
72 const int ArgumentReg0 = 8;
73 const int ArgumentReg1 = 9;
74 const int ArgumentReg2 = 10;
75 const int ArgumentReg3 = 11;
76 const int ArgumentReg4 = 12;
77 const int ArgumentReg5 = 13;
78 // Some OS syscall use a second register (o1) to return a second value
79 const int SyscallPseudoReturnReg = ArgumentReg1;
80
81 //XXX These numbers are bogus
82 const int MaxInstSrcRegs = 8;
83 const int MaxInstDestRegs = 9;
84
85 //8K. This value is implmentation specific; and should probably
86 //be somewhere else.
87 const int LogVMPageSize = 13;
88 const int VMPageSize = (1 << LogVMPageSize);
89
90 //Why does both the previous set of constants and this one exist?
91 const int PageShift = 13;
92 const int PageBytes = ULL(1) << PageShift;
93
94 const int BranchPredAddrShiftAmt = 2;
95
|
123 const int MachineBytes = 8;
124 const int WordBytes = 4;
125 const int HalfwordBytes = 2;
126 const int ByteBytes = 1;
127
128 void serialize(std::ostream & os);
129
130 void unserialize(Checkpoint *cp, const std::string §ion);
131
| |
132 StaticInstPtr decodeInst(ExtMachInst);
| 96 StaticInstPtr decodeInst(ExtMachInst);
|
133
134 // return a no-op instruction... used for instruction fetch faults
135 extern const MachInst NoopMachInst;
| |
136}
137
138#endif // __ARCH_SPARC_ISA_TRAITS_HH__
| 97}
98
99#endif // __ARCH_SPARC_ISA_TRAITS_HH__
|