1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
32#define __ARCH_SPARC_ISA_TRAITS_HH__
33
34#include "arch/sparc/types.hh"
35#include "base/misc.hh"
36#include "config/full_system.hh"
37#include "sim/host.hh"
38
39class ThreadContext;
40class FastCPU;
41//class FullCPU;
42class Checkpoint;
43
44class StaticInst;
45class StaticInstPtr;
46
47namespace BigEndianGuest {}
48
49#if FULL_SYSTEM
50#include "arch/sparc/isa_fullsys_traits.hh"
51#endif
52
53namespace SparcISA
54{
55 class RegFile;
56
57 //This makes sure the big endian versions of certain functions are used.
58 using namespace BigEndianGuest;
59
60 // SPARC have a delay slot
61 #define ISA_HAS_DELAY_SLOT 1
62
63 // SPARC NOP (sethi %(hi(0), g0)
64 const MachInst NoopMachInst = 0x01000000;
65
66 const int NumIntRegs = 32;
67 const int NumFloatRegs = 64;
68 const int NumMiscRegs = 40;
69
70 // These enumerate all the registers for dependence tracking.
71 enum DependenceTags {
72 // 0..31 are the integer regs 0..31
73 // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
74 FP_Base_DepTag = NumIntRegs,
75 Ctrl_Base_DepTag = NumIntRegs + NumFloatRegs,
76 //XXX These are here solely to get compilation and won't work
77 Fpcr_DepTag = 0,
78 Uniq_DepTag = 0
79 };
80
81
82 // MAXTL - maximum trap level
83 const int MaxPTL = 2;
84 const int MaxTL = 6;
85 const int MaxGL = 3;
86 const int MaxPGL = 2;
87
88 // NWINDOWS - number of register windows, can be 3 to 32
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
32#define __ARCH_SPARC_ISA_TRAITS_HH__
33
34#include "arch/sparc/types.hh"
35#include "base/misc.hh"
36#include "config/full_system.hh"
37#include "sim/host.hh"
38
39class ThreadContext;
40class FastCPU;
41//class FullCPU;
42class Checkpoint;
43
44class StaticInst;
45class StaticInstPtr;
46
47namespace BigEndianGuest {}
48
49#if FULL_SYSTEM
50#include "arch/sparc/isa_fullsys_traits.hh"
51#endif
52
53namespace SparcISA
54{
55 class RegFile;
56
57 //This makes sure the big endian versions of certain functions are used.
58 using namespace BigEndianGuest;
59
60 // SPARC have a delay slot
61 #define ISA_HAS_DELAY_SLOT 1
62
63 // SPARC NOP (sethi %(hi(0), g0)
64 const MachInst NoopMachInst = 0x01000000;
65
66 const int NumIntRegs = 32;
67 const int NumFloatRegs = 64;
68 const int NumMiscRegs = 40;
69
70 // These enumerate all the registers for dependence tracking.
71 enum DependenceTags {
72 // 0..31 are the integer regs 0..31
73 // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
74 FP_Base_DepTag = NumIntRegs,
75 Ctrl_Base_DepTag = NumIntRegs + NumFloatRegs,
76 //XXX These are here solely to get compilation and won't work
77 Fpcr_DepTag = 0,
78 Uniq_DepTag = 0
79 };
80
81
82 // MAXTL - maximum trap level
83 const int MaxPTL = 2;
84 const int MaxTL = 6;
85 const int MaxGL = 3;
86 const int MaxPGL = 2;
87
88 // NWINDOWS - number of register windows, can be 3 to 32
|
90
91 // semantically meaningful register indices
92 const int ZeroReg = 0; // architecturally meaningful
93 // the rest of these depend on the ABI
94 const int StackPointerReg = 14;
95 const int ReturnAddressReg = 31; // post call, precall is 15
96 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
97 const int FramePointerReg = 30;
98 const int ArgumentReg0 = 8;
99 const int ArgumentReg1 = 9;
100 const int ArgumentReg2 = 10;
101 const int ArgumentReg3 = 11;
102 const int ArgumentReg4 = 12;
103 const int ArgumentReg5 = 13;
104 // Some OS syscall use a second register (o1) to return a second value
105 const int SyscallPseudoReturnReg = ArgumentReg1;
106
107 //XXX These numbers are bogus
108 const int MaxInstSrcRegs = 8;
109 const int MaxInstDestRegs = 9;
110
111 //8K. This value is implmentation specific; and should probably
112 //be somewhere else.
113 const int LogVMPageSize = 13;
114 const int VMPageSize = (1 << LogVMPageSize);
115
116 //Why does both the previous set of constants and this one exist?
117 const int PageShift = 13;
118 const int PageBytes = ULL(1) << PageShift;
119
120 const int BranchPredAddrShiftAmt = 2;
121
122 const int MachineBytes = 8;
123 const int WordBytes = 4;
124 const int HalfwordBytes = 2;
125 const int ByteBytes = 1;
126
127 void serialize(std::ostream & os);
128
129 void unserialize(Checkpoint *cp, const std::string §ion);
130
131 StaticInstPtr decodeInst(ExtMachInst);
132
133 // return a no-op instruction... used for instruction fetch faults
134 extern const MachInst NoopMachInst;
135}
136
137#endif // __ARCH_SPARC_ISA_TRAITS_HH__
| 90
91 // semantically meaningful register indices
92 const int ZeroReg = 0; // architecturally meaningful
93 // the rest of these depend on the ABI
94 const int StackPointerReg = 14;
95 const int ReturnAddressReg = 31; // post call, precall is 15
96 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
97 const int FramePointerReg = 30;
98 const int ArgumentReg0 = 8;
99 const int ArgumentReg1 = 9;
100 const int ArgumentReg2 = 10;
101 const int ArgumentReg3 = 11;
102 const int ArgumentReg4 = 12;
103 const int ArgumentReg5 = 13;
104 // Some OS syscall use a second register (o1) to return a second value
105 const int SyscallPseudoReturnReg = ArgumentReg1;
106
107 //XXX These numbers are bogus
108 const int MaxInstSrcRegs = 8;
109 const int MaxInstDestRegs = 9;
110
111 //8K. This value is implmentation specific; and should probably
112 //be somewhere else.
113 const int LogVMPageSize = 13;
114 const int VMPageSize = (1 << LogVMPageSize);
115
116 //Why does both the previous set of constants and this one exist?
117 const int PageShift = 13;
118 const int PageBytes = ULL(1) << PageShift;
119
120 const int BranchPredAddrShiftAmt = 2;
121
122 const int MachineBytes = 8;
123 const int WordBytes = 4;
124 const int HalfwordBytes = 2;
125 const int ByteBytes = 1;
126
127 void serialize(std::ostream & os);
128
129 void unserialize(Checkpoint *cp, const std::string §ion);
130
131 StaticInstPtr decodeInst(ExtMachInst);
132
133 // return a no-op instruction... used for instruction fetch faults
134 extern const MachInst NoopMachInst;
135}
136
137#endif // __ARCH_SPARC_ISA_TRAITS_HH__
|