operands.isa (7799:5d0f62927d75) operands.isa (8449:4be49ad47c74)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31def operand_types {{
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31def operand_types {{
32 'sb' : ('signed int', 8),
33 'ub' : ('unsigned int', 8),
34 'shw' : ('signed int', 16),
35 'uhw' : ('unsigned int', 16),
36 'sw' : ('signed int', 32),
37 'uw' : ('unsigned int', 32),
38 'sdw' : ('signed int', 64),
39 'udw' : ('unsigned int', 64),
40 'tudw' : ('twin64 int', 64),
41 'tuw' : ('twin32 int', 32),
42 'sf' : ('float', 32),
43 'df' : ('float', 64),
44 'qf' : ('float', 128)
32 'sb' : 'int8_t',
33 'ub' : 'uint8_t',
34 'shw' : 'int16_t',
35 'uhw' : 'uint16_t',
36 'sw' : 'int32_t',
37 'uw' : 'uint32_t',
38 'sdw' : 'int64_t',
39 'udw' : 'uint64_t',
40 'tudw' : 'Twin64_t',
41 'tuw' : 'Twin32_t',
42 'sf' : 'float',
43 'df' : 'double'
45}};
46
47output header {{
48 // A function to "decompress" double and quad floating point
49 // register numbers stuffed into 5 bit fields. These have their
50 // MSB put in the LSB position but are otherwise normal.
51 static inline unsigned int
52 dfpr(unsigned int regNum)

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45
46output header {{
47 // A function to "decompress" double and quad floating point
48 // register numbers stuffed into 5 bit fields. These have their
49 // MSB put in the LSB position but are otherwise normal.
50 static inline unsigned int
51 dfpr(unsigned int regNum)

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