operands.isa (7790:9df469679ac7) | operands.isa (7799:5d0f62927d75) |
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1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 58 unchanged lines hidden (view full) --- 67 } 68}}; 69 70def operands {{ 71 # Int regs default to unsigned, but code should not count on this. 72 # For clarity, descriptions that depend on unsigned behavior should 73 # explicitly specify '.uq'. 74 | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 58 unchanged lines hidden (view full) --- 67 } 68}}; 69 70def operands {{ 71 # Int regs default to unsigned, but code should not count on this. 72 # For clarity, descriptions that depend on unsigned behavior should 73 # explicitly specify '.uq'. 74 |
75 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), | 75 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), |
76 # The Rd from the previous window | 76 # The Rd from the previous window |
77 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), | 77 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), |
78 # The Rd from the next window | 78 # The Rd from the next window |
79 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), | 79 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), |
80 # For microcoded twin load instructions, RdTwin appears in the "code" 81 # for the instruction is replaced by RdLow or RdHigh by the format 82 # before it's processed by the iop. 83 # The low (even) register of a two register pair | 80 # For microcoded twin load instructions, RdTwin appears in the "code" 81 # for the instruction is replaced by RdLow or RdHigh by the format 82 # before it's processed by the iop. 83 # The low (even) register of a two register pair |
84 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), | 84 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), |
85 # The high (odd) register of a two register pair | 85 # The high (odd) register of a two register pair |
86 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 87 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 88 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), | 86 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5), 87 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 88 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), |
89 # A microcode register. Right now, this is the only one. | 89 # A microcode register. Right now, this is the only one. |
90 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), | 90 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), |
91 # Because double and quad precision register numbers are decoded 92 # differently, they get different operands. The single precision versions 93 # have an s post pended to their name. | 91 # Because double and quad precision register numbers are decoded 92 # differently, they get different operands. The single precision versions 93 # have an s post pended to their name. |
94 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 95 #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 96 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 97 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), | 94 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 95 #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 96 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 97 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), |
98 # Each Frd_N refers to the Nth double precision register from Frd. 99 # Note that this adds twice N to the register number. | 98 # Each Frd_N refers to the Nth double precision register from Frd. 99 # Note that this adds twice N to the register number. |
100 #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 101 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 102 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 103 #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 104 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 105 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 106 #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 107 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 108 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 109 #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 110 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 111 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 112 #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 113 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 114 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 115 #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 116 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 117 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 118 #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 119 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 120 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 121 #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 122 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 123 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 124 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 125 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 126 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 127 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 128 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 129 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 130 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 131 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), | 100 #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 101 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10), 102 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10), 103 #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 104 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10), 105 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10), 106 #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 107 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10), 108 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10), 109 #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 110 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10), 111 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10), 112 #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 113 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10), 114 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10), 115 #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 116 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10), 117 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10), 118 #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 119 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10), 120 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10), 121 #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 122 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10), 123 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10), 124 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11), 125 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 126 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11), 127 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11), 128 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12), 129 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 130 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12), 131 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12), |
132 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), 133 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), 134 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), 135 # Registers which are used explicitly in instructions | 132 'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30), 133 'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30), 134 'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30), 135 # Registers which are used explicitly in instructions |
136 'R0': ('IntReg', 'udw', '0', None, 6), 137 'R1': ('IntReg', 'udw', '1', None, 7), 138 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 139 'R16': ('IntReg', 'udw', '16', None, 9), | 136 'R0': ('IntReg', 'udw', '0', None, 6), 137 'R1': ('IntReg', 'udw', '1', None, 7), 138 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 139 'R16': ('IntReg', 'udw', '16', None, 9), |
140 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 141 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 142 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 143 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 144 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 145 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 146 147 # Control registers | 140 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10), 141 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11), 142 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12), 143 'O3': ('IntReg', 'udw', '11', 'IsInteger', 13), 144 'O4': ('IntReg', 'udw', '12', 'IsInteger', 14), 145 'O5': ('IntReg', 'udw', '13', 'IsInteger', 15), 146 147 # Control registers |
148# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 149# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 150 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 151 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 152 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 153 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 154 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 155 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 156# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), 157 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 158 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 159 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 160 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 161 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 162 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 163 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), | 148# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 149# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 150 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 151 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41), 152 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 153 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 154 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 155 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 156# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), 157 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 158 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 159 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 160 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 161 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 162 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 163 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), |
164 | 164 |
165 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 166 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 167 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 168 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 169 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 170 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 171 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 172 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 173 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 174 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 175# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 176# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 177# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 178# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 179# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 180 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 181 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 182 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 183 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 184 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), | 165 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 166 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 167 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 168 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 169 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 170 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 171 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 172 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 173 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 174 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62), 175# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 176# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 177# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 178# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 179# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 180 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 181 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 182 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 183 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 184 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67), |
185 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 186 | 185 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 186 |
187 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 188 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 189 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 190 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 191 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 192 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 193 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), | 187 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 188 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 189 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 190 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 191 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 192 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 193 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), |
194 | 194 |
195 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), | 195 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80), |
196 # Mem gets a large number so it's always last | 196 # Mem gets a large number so it's always last |
197 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) | 197 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) |
198 199}}; | 198 199}}; |