operands.isa (4641:7bfba41846c2) operands.isa (7720:65d338a8dba4)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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121 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
122 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
123 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
124 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
125 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
126 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
127 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
128 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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121 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
122 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
123 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
124 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
125 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
126 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
127 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
128 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
129 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
130 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
129 'PCS': ('PCState', 'udw', None, (None, None, 'IsControl'), 30),
131 # Registers which are used explicitly in instructions
132 'R0': ('IntReg', 'udw', '0', None, 6),
133 'R1': ('IntReg', 'udw', '1', None, 7),
134 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
135 'R16': ('IntReg', 'udw', '16', None, 9),
136 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
137 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
138 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),

--- 57 unchanged lines hidden --- 		130 # Registers which are used explicitly in instructions
131 'R0': ('IntReg', 'udw', '0', None, 6),
132 'R1': ('IntReg', 'udw', '1', None, 7),
133 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
134 'R16': ('IntReg', 'udw', '16', None, 9),
135 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),
136 'O1': ('IntReg', 'udw', '9', 'IsInteger', 11),
137 'O2': ('IntReg', 'udw', '10', 'IsInteger', 12),

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