operands.isa (4634:56ee30ecc1ba) operands.isa (4641:7bfba41846c2)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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144# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
145# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
146 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
147 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
148 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
149 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
150 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
151 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 135 unchanged lines hidden (view full) ---

144# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40),
145# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),
146 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40),
147 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
148 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
149 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
150 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
151 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
152 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46),
152# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46),
153 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46),
153 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
154 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
155 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
156 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
157 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
158 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
159
160 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),

--- 34 unchanged lines hidden --- 		154 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
155 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
156 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
157 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
158 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
159 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
160
161 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),

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