Cross Reference: /gem5/src/arch/sparc/isa/operands.isa

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operands.isa (4362:95e5f28ce484)	operands.isa (4634:56ee30ecc1ba)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 173 unchanged lines hidden (view full) --- 182 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 183 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 184 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 185 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 186 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 187 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 188 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 189	1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 173 unchanged lines hidden (view full) --- 182 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 183 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 184 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 185 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 186 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 187 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 188 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 189
190 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),	190 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
191 # Mem gets a large number so it's always last 192 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 193 194}};	191 # Mem gets a large number so it's always last 192 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 193 194}};