operands.isa (4115:cc1d6df13c7d) operands.isa (4362:95e5f28ce484)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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47output header {{
48 // A function to "decompress" double and quad floating point
49 // register numbers stuffed into 5 bit fields. These have their
50 // MSB put in the LSB position but are otherwise normal.
51 static inline unsigned int dfpr(unsigned int regNum)
52 {
53 return (regNum & (~1)) | ((regNum & 1) << 5);
54 }
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 38 unchanged lines hidden (view full) ---

47output header {{
48 // A function to "decompress" double and quad floating point
49 // register numbers stuffed into 5 bit fields. These have their
50 // MSB put in the LSB position but are otherwise normal.
51 static inline unsigned int dfpr(unsigned int regNum)
52 {
53 return (regNum & (~1)) | ((regNum & 1) << 5);
54 }
55
56 static inline unsigned int dfprl(unsigned int regNum)
57 {
58 return dfpr(regNum) & (~0x1);
59 }
60
61 static inline unsigned int dfprh(unsigned int regNum)
62 {
63 return dfpr(regNum) | 0x1;
64 }
55}};
56
57def operands {{
58 # Int regs default to unsigned, but code should not count on this.
59 # For clarity, descriptions that depend on unsigned behavior should
60 # explicitly specify '.uq'.
61
62 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),

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74 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
75 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
76 # A microcode register. Right now, this is the only one.
77 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
78 # Because double and quad precision register numbers are decoded
79 # differently, they get different operands. The single precision versions
80 # have an s post pended to their name.
81 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
65}};
66
67def operands {{
68 # Int regs default to unsigned, but code should not count on this.
69 # For clarity, descriptions that depend on unsigned behavior should
70 # explicitly specify '.uq'.
71
72 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),

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84 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
85 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
86 # A microcode register. Right now, this is the only one.
87 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8),
88 # Because double and quad precision register numbers are decoded
89 # differently, they get different operands. The single precision versions
90 # have an s post pended to their name.
91 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
82 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
92 #'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
93 'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
94 'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
83 # Each Frd_N refers to the Nth double precision register from Frd.
84 # Note that this adds twice N to the register number.
95 # Each Frd_N refers to the Nth double precision register from Frd.
96 # Note that this adds twice N to the register number.
85 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
86 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
87 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
88 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
89 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
90 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
91 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
92 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
97 #'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
98 'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
99 'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
100 #'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
101 'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
102 'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
103 #'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
104 'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
105 'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
106 #'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
107 'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
108 'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
109 #'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
110 'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
111 'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
112 #'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
113 'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
114 'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
115 #'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
116 'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
117 'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
118 #'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
119 'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
120 'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
93 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
121 'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
94 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
122 #'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
123 'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
124 'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
95 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
125 'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
96 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
126 #'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
127 'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
128 'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
97 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
98 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
99 # Registers which are used explicitly in instructions
100 'R0': ('IntReg', 'udw', '0', None, 6),
101 'R1': ('IntReg', 'udw', '1', None, 7),
102 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
103 'R16': ('IntReg', 'udw', '16', None, 9),
104 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),

--- 58 unchanged lines hidden --- 		129 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
130 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
131 # Registers which are used explicitly in instructions
132 'R0': ('IntReg', 'udw', '0', None, 6),
133 'R1': ('IntReg', 'udw', '1', None, 7),
134 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
135 'R16': ('IntReg', 'udw', '16', None, 9),
136 'O0': ('IntReg', 'udw', '8', 'IsInteger', 10),

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