operands.isa (3761:b7c7f547d5a3) operands.isa (3793:0e13f3c9bec4)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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118 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
119 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
120 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
121 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
122 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
123 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
124 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
125 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 109 unchanged lines hidden (view full) ---

118 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
119 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
120 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
121 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
122 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
123 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59),
124 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
125 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
126 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing']), 62),
126 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 62),
127# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
128# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
129# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
130# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
131# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
132 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
133 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
134 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),

--- 17 unchanged lines hidden --- 		127# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63),
128# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64),
129# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65),
130# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66),
131# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),
132 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63),
133 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64),
134 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65),

--- 17 unchanged lines hidden ---