Cross Reference: /gem5/src/arch/sparc/isa/operands.isa

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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 42 unchanged lines hidden (view full) --- 51 return (regNum & (~1)) \| ((regNum & 1) << 5); 52 } 53}}; 54 55def operands {{ 56 # Int regs default to unsigned, but code should not count on this. 57 # For clarity, descriptions that depend on unsigned behavior should 58 # explicitly specify '.uq'.	1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 42 unchanged lines hidden (view full) --- 51 return (regNum & (~1)) \| ((regNum & 1) << 5); 52 } 53}}; 54 55def operands {{ 56 # Int regs default to unsigned, but code should not count on this. 57 # For clarity, descriptions that depend on unsigned behavior should 58 # explicitly specify '.uq'.
	59
59 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),	60 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
60 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), 61 'RdHigh': ('IntReg', 'udw', 'RD \| 1', 'IsInteger', 3), 62 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), 63 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), 64 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 6),	61 # The Rd from the previous window 62 'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2), 63 # The Rd from the next window 64 'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3), 65 # The low (even) register of a two register pair 66 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4), 67 # The high (odd) register of a two register pair 68 'RdHigh': ('IntReg', 'udw', 'RD \| 1', 'IsInteger', 5), 69 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6), 70 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7), 71 # A microcode register. Right now, this is the only one. 72 'uReg0': ('IntReg', 'udw', 'NumIntArchRegs', 'IsInteger', 8), 73 # Because double and quad precision register numbers are decoded 74 # differently, they get different operands. The single precision versions 75 # have an s post pended to their name.
65 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 66 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 67 # Each Frd_N refers to the Nth double precision register from Frd. 68 # Note that this adds twice N to the register number. 69 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 70 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 71 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 72 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 73 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 74 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 75 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 76 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 77 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 78 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 79 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 80 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),	76 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10), 77 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 78 # Each Frd_N refers to the Nth double precision register from Frd. 79 # Note that this adds twice N to the register number. 80 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10), 81 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10), 82 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10), 83 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10), 84 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 85 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 86 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 87 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 88 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 89 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 90 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 91 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 92 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 93 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
	94 # Registers which are used explicitly in instructions
83 'R0': ('IntReg', 'udw', '0', None, 6), 84 'R1': ('IntReg', 'udw', '1', None, 7), 85 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 86 'R16': ('IntReg', 'udw', '16', None, 9), 87 88 # Control registers	95 'R0': ('IntReg', 'udw', '0', None, 6), 96 'R1': ('IntReg', 'udw', '1', None, 7), 97 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 98 'R16': ('IntReg', 'udw', '16', None, 9), 99 100 # Control registers
89 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 90 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41),	101# 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 102# 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 103 'Y': ('IntReg', 'udw', 'NumIntArchRegs + 1', None, 40), 104 'Ccr': ('IntReg', 'udw', 'NumIntArchRegs + 2', None, 41),
91 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 92 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 93 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 94 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 95 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), 96 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 97 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 98 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), --- 5 unchanged lines hidden (view full) --- 104 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 105 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 106 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 107 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 108 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 109 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 110 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 111 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),	105 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 106 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 107 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 108 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 109 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), 110 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 111 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 112 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), --- 5 unchanged lines hidden (view full) --- 118 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 119 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 120 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 121 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 122 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 123 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 124 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 125 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
112 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62), 113 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 114 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 115 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 116 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 117 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67),	126 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', (None, None, ['IsSerializeAfter','IsSerializing']), 62), 127# 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 128# 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 129# 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 130# 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 131# 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 132 'Cansave': ('IntReg', 'udw', 'NumIntArchRegs + 3', None, 63), 133 'Canrestore': ('IntReg', 'udw', 'NumIntArchRegs + 4', None, 64), 134 'Cleanwin': ('IntReg', 'udw', 'NumIntArchRegs + 5', None, 65), 135 'Otherwin': ('IntReg', 'udw', 'NumIntArchRegs + 6', None, 66), 136 'Wstate': ('IntReg', 'udw', 'NumIntArchRegs + 7', None, 67),
118 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 119 120 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 121 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 122 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 123 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 124 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 125 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 126 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 127 128 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), 129 # Mem gets a large number so it's always last 130 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 131 132}};	137 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), 138 139 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 140 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 141 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 142 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 143 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 144 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), 145 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75), 146 147 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), 148 # Mem gets a large number so it's always last 149 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 150 151}};