operands.isa (3587:841cf134f321) operands.isa (3600:885979c36aa4)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 109 unchanged lines hidden (view full) ---

118 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
119
120 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
121 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
122 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
123 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
124 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
125 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 109 unchanged lines hidden (view full) ---

118 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
119
120 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69),
121 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
122 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
123 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
124 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
125 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
126 'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
126
127 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
128 # Mem gets a large number so it's always last
129 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
130
131}};
127
128 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
129 # Mem gets a large number so it's always last
130 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
131
132}};