operands.isa (3437:96977e433be6) | operands.isa (3587:841cf134f321) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 66 unchanged lines hidden (view full) --- 75 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 76 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 77 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 78 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 79 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 80 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 66 unchanged lines hidden (view full) --- 75 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 76 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 77 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 78 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 79 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 80 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12), 81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), |
83 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 84 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), | |
85 'R0': ('IntReg', 'udw', '0', None, 6), 86 'R1': ('IntReg', 'udw', '1', None, 7), 87 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 88 'R16': ('IntReg', 'udw', '16', None, 9), 89 90 # Control registers 91 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 92 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 93 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), | 83 'R0': ('IntReg', 'udw', '0', None, 6), 84 'R1': ('IntReg', 'udw', '1', None, 7), 85 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 86 'R16': ('IntReg', 'udw', '16', None, 9), 87 88 # Control registers 89 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 90 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 91 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), |
92 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 93 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 94 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), 95 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), 96 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 97 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 98 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), 99 'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50), 100 'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51), 101 'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52), |
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94 | 102 |
95 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 96 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 97 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 98 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), 99 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47), 100 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48), | 103 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53), 104 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54), 105 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55), 106 'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56), 107 'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57), 108 'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58), 109 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 59), 110 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60), 111 'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61), 112 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 62), 113 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 63), 114 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 64), 115 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 65), 116 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 66), 117 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 67), 118 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68), |
101 | 119 |
102 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49), 103 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50), 104 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51), 105 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52), 106 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53), 107 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54), 108 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55), | 120 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 69), 121 'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70), 122 'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71), 123 'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72), 124 'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73), 125 'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74), |
109 | 126 |
110 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56), 111 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57), | 127 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 80), |
112 # Mem gets a large number so it's always last 113 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 114 115}}; | 128 # Mem gets a large number so it's always last 129 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 130 131}}; |