operands.isa (3418:50e5c0cb3186) operands.isa (3437:96977e433be6)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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56 # Int regs default to unsigned, but code should not count on this.
57 # For clarity, descriptions that depend on unsigned behavior should
58 # explicitly specify '.uq'.
59 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
60 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
61 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
62 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
63 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 47 unchanged lines hidden (view full) ---

56 # Int regs default to unsigned, but code should not count on this.
57 # For clarity, descriptions that depend on unsigned behavior should
58 # explicitly specify '.uq'.
59 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
60 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
61 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
62 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
63 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
64 'uReg0': ('IntReg', 'udw', 'NumRegularIntRegs+0', 'IsInteger', 6),
64 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
65 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
66 # Each Frd_N refers to the Nth double precision register from Frd.
67 # Note that this adds twice N to the register number.
68 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
69 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
70 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
71 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),

--- 43 unchanged lines hidden --- 		65 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
66 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
67 # Each Frd_N refers to the Nth double precision register from Frd.
68 # Note that this adds twice N to the register number.
69 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
70 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
71 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
72 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),

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