operands.isa (3388:1c6ebfc4c20e) | operands.isa (3418:50e5c0cb3186) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 81 unchanged lines hidden (view full) --- 90 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 91 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 92 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 93 94 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 95 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 96 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 97 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 81 unchanged lines hidden (view full) --- 90 'Y': ('ControlReg', 'udw', 'MISCREG_Y', None, 40), 91 'Ccr': ('ControlReg', 'udw', 'MISCREG_CCR', None, 41), 92 'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42), 93 94 'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 43), 95 'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44), 96 'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45), 97 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46), |
98 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47), | 98 'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47), 99 'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48), |
99 | 100 |
100 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48), 101 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 102 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 103 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 104 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 105 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 106 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), | 101 'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49), 102 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50), 103 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51), 104 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52), 105 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53), 106 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54), 107 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55), |
107 | 108 |
108 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55), 109 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56), | 109 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56), 110 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57), |
110 # Mem gets a large number so it's always last 111 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 112 113}}; | 111 # Mem gets a large number so it's always last 112 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100) 113 114}}; |