Cross Reference: /gem5/src/arch/sparc/isa/operands.isa

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operands.isa (3381:0897959bf0e0)	operands.isa (3388:1c6ebfc4c20e)
1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 63 unchanged lines hidden (view full) --- 72 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 73 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 74 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 75 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 76 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 77 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 78 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 79 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),	1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 63 unchanged lines hidden (view full) --- 72 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10), 73 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10), 74 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10), 75 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10), 76 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11), 77 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11), 78 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12), 79 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
80 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 83 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 84 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 85 'R0': ('IntReg', 'udw', '0', None, 6), 86 'R1': ('IntReg', 'udw', '1', None, 7), 87 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 88 'R16': ('IntReg', 'udw', '16', None, 9), --- 13 unchanged lines hidden (view full) --- 102 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 103 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 104 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 105 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 106 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 107 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 108 109 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),	80 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31), 81 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32), 82 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), 83 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 84 'R0': ('IntReg', 'udw', '0', None, 6), 85 'R1': ('IntReg', 'udw', '1', None, 7), 86 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), 87 'R16': ('IntReg', 'udw', '16', None, 9), --- 13 unchanged lines hidden (view full) --- 101 'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49), 102 'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50), 103 'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51), 104 'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52), 105 'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53), 106 'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54), 107 108 'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
110 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56)	109 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56), 110 # Mem gets a large number so it's always last 111 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
111 112}};	112 113}};