operands.isa (3272:c28038eaefb8) operands.isa (3279:cf42adf4588f)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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37 'uw' : ('unsigned int', 32),
38 'sdw' : ('signed int', 64),
39 'udw' : ('unsigned int', 64),
40 'sf' : ('float', 32),
41 'df' : ('float', 64),
42 'qf' : ('float', 128)
43}};
44
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 28 unchanged lines hidden (view full) ---

37 'uw' : ('unsigned int', 32),
38 'sdw' : ('signed int', 64),
39 'udw' : ('unsigned int', 64),
40 'sf' : ('float', 32),
41 'df' : ('float', 64),
42 'qf' : ('float', 128)
43}};
44
45output header {{
46 // A function to "decompress" double and quad floating point
47 // register numbers stuffed into 5 bit fields. These have their
48 // MSB put in the LSB position but are otherwise normal.
49 static inline unsigned int dfpr(unsigned int regNum)
50 {
51 return regNum | ((regNum & 1) << 5);
52 }
53}};
54
45def operands {{
46 # Int regs default to unsigned, but code should not count on this.
47 # For clarity, descriptions that depend on unsigned behavior should
48 # explicitly specify '.uq'.
49 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
50 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
51 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
52 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
53 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
55def operands {{
56 # Int regs default to unsigned, but code should not count on this.
57 # For clarity, descriptions that depend on unsigned behavior should
58 # explicitly specify '.uq'.
59 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
60 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
61 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
62 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
63 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
54 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
55 'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
56 'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10),
57 'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10),
58 'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10),
59 'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10),
60 'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10),
61 'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10),
62 'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10),
63 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
64 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
64 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
65 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
66 # Each Frd_N refers to the Nth double precision register from Frd.
67 # Note that this adds twice N to the register number.
68 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
69 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
70 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
71 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
72 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
73 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
74 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
75 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
76 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
77 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
78 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
79 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
65 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
66 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
67 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
68 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
69 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
70 'R0': ('IntReg', 'udw', '0', None, 6),
71 'R1': ('IntReg', 'udw', '1', None, 7),
72 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),

--- 25 unchanged lines hidden --- 		80 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
81 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
82 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
83 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
84 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
85 'R0': ('IntReg', 'udw', '0', None, 6),
86 'R1': ('IntReg', 'udw', '1', None, 7),
87 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),

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