operands.isa (2962:4f3ee6fa65fa) operands.isa (3272:c28038eaefb8)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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47 # For clarity, descriptions that depend on unsigned behavior should
48 # explicitly specify '.uq'.
49 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
50 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
51 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
52 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
53 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
54 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 38 unchanged lines hidden (view full) ---

47 # For clarity, descriptions that depend on unsigned behavior should
48 # explicitly specify '.uq'.
49 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
50 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
51 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
52 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
53 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
54 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
55 'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
56 'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10),
57 'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10),
58 'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10),
59 'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10),
60 'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10),
61 'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10),
62 'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10),
55 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
56 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
57 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
58 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
59 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
60 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
61 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
62 'R0': ('IntReg', 'udw', '0', None, 6),

--- 27 unchanged lines hidden --- 		63 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
64 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
65 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
66 'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
67 'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),
68 #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
69 #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
70 'R0': ('IntReg', 'udw', '0', None, 6),

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